EGR426 W’10Learning Activity #15Objectives• To practice working with fixed-point numbersPart I – Signed Fractional Numbe rsUse the following interpretation of sig ned, fixed-point 8-bit fractional numbers:−202−12−22−32−42−52−62−7Compute the following:1. The fractional representation of 0.93752. The fractional representation of 0.9 (as close as you c an get)3. The fractional representation of -0.93754. The two’s complement of your answer to part #1 (i.e., invert all the bits then add 1 as if you wereadding integers). Compare with your answer to part #3.5. The fractional representation of -0.9 (as close as you can get)Part II – Printing Fractional Numbers1. Create a new Xilinx ISE project named ’la15’. Type in the program shown below and add it to theproject as ’la15.vhd’. Note that Xilinx ISE will recognize that this is a simulation-only progr am (ithas no I/O pins) thus will add it to the Behavioral Simulation set of sources. You won’t be able toSynthesize or Implement this project (and you don’t need to).This program introduces you to the VHDL REAL data type, which is only suppo rted in simulation.2. Before running the program, predict the output.3. Simulate the program. Note the re sults are printed in the Simulation Conso le window at the bottomof the screen – the timing display is not useful.Verify the results against your predictions.LIBRARY IEEE ;USE i e e e . std_lo gic_11 64 . a l l ;USE i e e e . numeric_std . a l l ;USE st d . t e x t i o . a l l ;USE i e e e . s t d _ l o g i c _ t e x ti o . a l l ;ENTITY t e s t ISEND ENTITY t e s t ;ARCHITECTURE a OF t e s t ISFUNCTION Fr a c t2Real ( va lue : s td _l og i c _ve c to r ( 7 downto 0 ) ) RETURN r e a l IS1VARIABLE toadd , sum : r e a l ;BEGINtoadd := 1 . 0 / ( 2 . 0 ∗ ∗ value ’ l e f t ) ; −− i . e . , 2^(− 7)sum := 0 . 0 ;FOR I IN 0 TO ( value ’ l e f t − 1) LOOPIF v alu e ( I )= ’1 ’ THENsum := sum + toadd ;END IF ;toadd := toadd ∗ 2 . 0 ;END LOOP;IF v alu e ( value ’ l e f t )= ’1 ’ THENsum := sum − 1 . 0 ;END IF ;RETURN sum ;END FUNCTION F r a c t2Real ;SIGNAL t e s t s i g : s td _ lo g ic _v ec to r (7 downto 0 ) ;BEGINPROCESSBEGINt e s t s i g <= "0 1 0 1 0 1 0 1 " ; WAIT FOR 1 ns ;REPORT "01010101 => " & r e a l ’ image ( Fract 2 Real ( t e s t s i g ) ) ;t e s t s i g <= "0 1 1 1 1 1 1 1 " ; WAIT FOR 1 ns ;REPORT "01111111 => " & r e a l ’ image ( Fract 2 Real ( t e s t s i g ) ) ;t e s t s i g <= "1 1 1 1 1 1 1 1 " ; WAIT FOR 1 ns ;REPORT "11111111 => " & r e a l ’ image ( Fract 2 Real ( t e s t s i g ) ) ;t e s t s i g <= "1 0 0 0 0 0 0 0 " ; WAIT FOR 1 ns ;REPORT "10000000 => " & r e a l ’ image ( Fract 2 Real ( t e s t s i g ) ) ;WAIT;END PROCESS;END ARCHITECTURE a