EGR426 W’10Learning Activity #13Objective• Investigate the various tradeoffs in a dder implementationsOverviewYou will implement several architectural varieties of a full adder. You will vary the number of bits in theadder and will synthesize the design to determine the number of LUT’s required and the maximum delaythrough the adder. We will then compare the four architectures.The Common Framework1. Create the following top-level VHD file la13.vhd:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY LA13 ISGENERIC (WIDTH : INTEGER := 16);PORT (A, B : IN UNSIGNED(WIDTH-1 DOWNTO 0);X : OUT UNSIGNED(WIDTH-1 DOWNTO 0));END ENTITY LA13;2. Create a new project na med LA13 with the la13.vhd file as the top-level entity. NOTE: For thisproject you must assign the XC3S1600E device in the Spartan-3E family. We a re going touse a “big” FPGA to synthesize a “big” adder. Also specify the FG484 package in the -5 speed grade.Part I – Behavioral and Hope For The Best1. You will let Xilinx ISE infer logic for an adder a s it sees fit. The architecture for your adder shouldsimply be:X <= A+B;2. Ensure you have chosen the XC3S1600E device in the Spartan-3E family (it has 29504 LUT’s!) YourSources window s hould show your project as residing on a xc3s1600e-5fg484 device.3. Run Synthesize then Implement Design with WIDTH=16 bits (i.e., as written above). Note the LUTusage on the summary page of the Design Summary. Also note the worst-case propagation delay fromA/B to X (tP D) – this is in the Sta tic Timing Repo rt section of the Design Summa ry . Enter thesetwo values in a spreadsheet.4. Vary the WIDTH generic in increments of 32 (16, 48, 80, etc.) until the desig n will no longer fit intothe device. Did you run out of L UT’s or pins? For each WIDTH, recor d the LUT usage and worst-case pro pagation delay (you don’t have to look through every line of the Static Timing Report....just“eyeball” the worst-case).1Part II – Ripple Adder1. You will implement a set of cascaded 1-bit ripple adders...as slow as it gets. Your architecture will be(following the equations on page 103 of your lecture notes):PROCESS (A,B)VARIABLE C : STD_LOGIC;BEGINC := ’0’;FOR I IN 0 TO X’LEFT LOOPX(I) <= A(I) XOR B(I) XOR C;C := (A(I) AND B(I)) OR (C AND (A(I) OR B(I)));END LOOP;END PROCESS;2. Compile your design with WIDTH=16 bits. Note the LUT usage and the worst-case propagation delay(in the Static Timing Report section of the Design Summary) from A/B to X (tP D). Enter these in aspreadsheet.3. Vary the WIDTH generic in increments of 32 (16, 48, 80, etc.) until the desig n will no longer fit intothe device. Did you run out of LUT’s or pins?Part III – Carry Lookahead Generator1. You will implement a separate VHDL fast lookahead carry generator component. To decla re thiscomponent in your architecture:COMPONENT CGEN ISGENERIC( WIDTH : INTEGER);PORT(A, B : IN UNSIGNED(WIDTH-1 DOWNTO 0);CVEC : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));END COMPONENT CGEN;SIGNAL CVEC : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);The implementation of the adder will be (implementing Figure 4 on page 106 of the lectur e notes):U1: CGENGENERIC MAP(WIDTH => WIDTH)PORT MAP(A, B, CVEC);PROCESS (A,B,CVEC)BEGINFOR I IN 0 TO X’LEFT LOOPX(I) <= A(I) XOR B(I) XOR CVEC(I);END LOOP;END PROCESS;2. The carry lookahead generator is implemented in a separate file, CGEN.VHD (implementing equationson page 103 of the lecture notes):LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;2USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY CGEN ISGENERIC( WIDTH : INTEGER := 16);PORT(A, B : IN UNSIGNED(WIDTH-1 DOWNTO 0);CVEC : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));END ENTITY CGEN;ARCHITECTURE a OF CGEN ISBEGINPROCESS (A,B)VARIABLE C : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);BEGINC(0) := ’0’;FOR I IN 1 TO WIDTH-1 LOOPC(I) := ((A(I-1) OR B(I-1)) AND C(I-1)) OR (A(I-1) AND B(I-1));END LOOP;CVEC <= C;END PROCESS;END ARCHITECTURE a;3. Compile your design with WIDTH=16 bits. Note the LUT usage and the worst-case propagation delay(in the Static Timing Report section of the Design Summary) from A/B to X (tP D). Enter these in aspreadsheet.4. Vary the WIDTH generic in increments of 32 (16, 48, 80, etc.) until the desig n will no longer fit intothe device. Did you run out of LUT’s or pins?Analysis1. Plot the LUT usag e of all 3 approaches on the sa me axes. Which approach has the minimum usage?2. Plot the tP Dof all 3 approaches on the same axes. Which approach has the minimum tP D?3. How do your results above correlate with the exp ected theoretical