0. General Information/Introduction0.1 The Group - Why and What0.2 What Is VHDL0.3 Before Posting0.4 Major Contributors to this FAQ0.5 Disclaimer1. Abbreviations2. Contacts and Archives2.1 Official ContactsAccelleraVHDL InternationalVHDL-AMS, 1076.1 Working GroupWAVES/TISSS2.2 VHDL User GroupsVHDL International Users Forum2.3 Archives3. VHDL on the Web3.1 Tutorials3.2 VHDL Models3.3 Magazines3.4 VHDL Sites4. Frequently Asked Questions4.1 About Changes to the VHDL Standard4.2 Language Related Questions4.2.1 USE of Library Elements?4.2.2 Component Instantiation and Default Component Binding4.2.3 GENERATE Usage and Configuration4.2.4 Aggregates/Arrays Containing a Single Element4.2.5 Operations With Array Aggregates4.2.6 How to Attach Attributes Inside of Generate4.2.7 Notes on Range Directions4.2.8 Integer - Time Conversion4.2.9 "Don't Cares" in VHDL4.2.10 How to Open and Close Files4.2.11 How to Read/Write Binary Files4.2.12 How to Use Package Textio for Accessing Text Files4.2.13 Signal Drivers4.2.14 Procedures and Drivers4.2.15 Case Statement4.2.16 How to Monitor Signals4.2.17 Resolving Ambiguous Procedure/Function/Operator Calls4.2.18 How to Resolve Type Ambiguities in Expressions4.2.19 How to Use Bit Strings as Argument to the To_StdLogicVector Function4.2.20 Conflicting Compare Operators4.2.21 How to Convert Between Enumeration and Integer Values4.2.22 How to Convert Between ASCII and Characters4.2.23 How to Convert Between Scalar Values and Strings4.2.24 How to Convert Bit/Std_Logic_Vectors to Strings4.2.25 How to Convert Between Integer and Bit/Std_Logic-Vectors4.2.26 How to Convert Between bit_vector, std_logic_vector, std_ulogic_vector, signed and unsigned4.2.27 Reduction Operators for Bit-Vectors4.2.28 Gray Code Counter Model4.2.29 Is There a printf†‡ Like Function in VHDL?4.2.30 How to Code a Clock Divider4.2.31 How to Stop Simulation4.2.32 Ports of Mode Buffer4.2.33 Multi-Dimensional Arrays4.2.34 Multi-Dimensional Array Literals4.2.35 Conditional Compilation4.2.36 Remarks on Visibility of Declarations4.2.37 Difference between std_logic and std_ulogic4.2.38 VHDL and Synthesis4.2.39 Locally and Globally Static4.2.40 Arithmetic Operations on Bit-Vectors4.2.41 VHDL'93 Generates Different Concatenation Results from VHDL'874.2.42 rising_edge†clk‡ versus †clk'event and clk='1'‡4.3 What do I Need to Generate Hardware from VHDL Models4.4 PUBLIC DOMAIN Tools?4.5 VHDL Validation Suite Available?4.6 Status of Analog VHDL †VHDL-AMS, 1076.1‡4.7 How Can People Get More Information about VHDL-AMS †1076.1‡4.8 Standards and Standard Packages4.8.1 Functions and Operators Defined in Package numeric_std4.9 Where to Obtain the comp.lang.vhdl FAQ4.10 "Frequently Requested" Models/Packages4.11 Arithmetic Packages for bit/std_logic-Vectors4.12 Where Can I Find More Infocomp.lang.vhdlFrequently Asked Questions And Answers (Part 1): GeneralPreliminary RemarksThis is a monthly posting to comp.lang.vhdl containing general information. Please sendadditional information directly to the editor: [email protected] (Edwin Naroska)Corrections and suggestions are appreciated. Thanks for all corrections. There are three other regular postings: part 2 lists books on VHDL, part 3 lists products andservices (PD+commercial), part 4 contains descriptions for a number of terms and phrases used todefine VHDL.Table of Contents............ 10. General Information/Introduction............ 10.1 The Group - Why and What............... 10.2 What Is VHDL............... 10.3 Before Posting............ 20.4 Major Contributors to this FAQ................ 20.5 Disclaimer................ 31. Abbreviations............... 42. Contacts and Archives............... 42.1 Official Contacts................. 4Accellera.............. 4VHDL International........... 4VHDL-AMS, 1076.1 Working Group............... 5WAVES/TISSS.............. 52.2 VHDL User Groups........... 5VHDL International Users Forum................. 62.3 Archives............... 73. VHDL on the Web................. 73.1 Tutorials............... 73.2 VHDL Models................ 93.3 Magazines................ 93.4 VHDL Sites............. 104. Frequently Asked Questions.......... 104.1 About Changes to the VHDL Standard............ 104.2 Language Related Questions............ 104.2.1 USE of Library Elements?..... 104.2.2 Component Instantiation and Default Component Binding......... 154.2.3 GENERATE Usage and Configuration....... 164.2.4 Aggregates/Arrays Containing a Single Element.......... 174.2.5 Operations With Array Aggregates........ 194.2.6 How to Attach Attributes Inside of Generate............ 194.2.7 Notes on Range Directions............ 204.2.8 Integer - Time Conversion............ 204.2.9 "Don’t Cares" in VHDL........... 214.2.10 How to Open and Close Files.......... 234.2.11 How to Read/Write Binary Files...... 234.2.12 How to Use Package Textio for Accessing Text Files.............. 274.2.13 Signal Drivers............ 304.2.14 Procedures and Drivers.............. 314.2.15 Case Statement............ 324.2.16 How to Monitor Signals- i -Table of ContentsFAQ comp.lang.vhdl (part 1) : General...... 334.2.17 Resolving Ambiguous Procedure/Function/Operator Calls....... 354.2.18 How to Resolve Type Ambiguities in Expressions.. 374.2.19 How to Use Bit Strings as Argument to the To_StdLogicVector Function............ 384.2.20 Conflicting Compare Operators...... 394.2.21 How to Convert Between Enumeration and Integer Values........ 414.2.22 How to Convert Between ASCII and Characters....... 414.2.23 How to Convert Between Scalar Values and Strings....... 424.2.24 How to Convert Bit/Std_Logic_Vectors to Strings..... 424.2.25 How to Convert Between Integer and Bit/Std_Logic-Vectors4.2.26 How to Convert Between bit_vector, std_logic_vector, std_ulogic_vector, signed................. 44and unsigned.......... 464.2.27 Reduction Operators for Bit-Vectors............. 474.2.28 Gray Code Counter Model......... 474.2.29 Is There a printf() Like Function in VHDL?............ 484.2.30 How to Code a Clock Divider............. 494.2.31 How to Stop Simulation.............. 504.2.32 Ports of Mode Buffer............. 514.2.33 Multi-Dimensional Arrays........... 524.2.34 Multi-Dimensional Array Literals............. 534.2.35 Conditional Compilation.......... 544.2.36 Remarks on Visibility of Declarations......... 574.2.37 Difference between std_logic and std_ulogic.............. 604.2.38 VHDL and Synthesis............ 634.2.39 Locally and