EGR426 W’10Learning Activity #14Objectives• To investigate various multiplication architecture implementationsPart I – Built-In Synthesis (SIGNED Multiplication)1. Create a new project named LA14 and create the following top-level VHDL file named “la14.vhd”.LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY LA14 ISPORT (A, B : IN SIGNED(7 downto 0);X : OUT SIGNED(15 downto 0));END ENTITY LA14;ARCHITECTURE a OF LA14 ISBEGINX <= A*B;END ARCHITECTURE a;2. Use the usual Spartan 3E XC3S500E device for this project. Synthesize and Implement your project.3. Note the worst-case propagation delay from inputs to outputs (Design Summary –> Static TimingReport). Note the LUT usage. Record these numbers in a spreadsheet under the heading “Built-InSynthesis: SIGNED”.4. Create a new Testbench Waveform file. Use the Pattern Wizard dialog (click in the timing windowafter about 100ns) to set the A bus to 0x23 and the B bus to 0x34.5. Verify that the multiplier works properly (HINT: 0x23==35, 0x3 4=52).6. Cha nge the A bus to be A=0xFF and repeat the simulation. Doe s it work properly? (HINT: 0xFF=-1in the 8-bit signed two’s complement interpretation).Part II – Built-In Synthesis (UNSIGNED Multiplication)1. Cha nge the type of the A, B, and X signals from SIGNED to UNSIGNED in the “la14.vhd” VHDLfile.2. Clean all of the project’s files by selecting Project->Cleanup Project Files. Once again, Synthesize andImplement the project. Note again the worst-case timing and LUT usage. Record your results underthe heading “Built-In Synthesis: UNSIGNED”.3. Create a new simulation Testbench Waveform (necessary since the types of the buses have changedfrom SIGNED to UNSIGNED). Repeat the simulation with A=0x23 and B=0x34. Does it s till work?4. Cha nge the A bus to be A=0xFF (which is 255 in the unsigned interpretation). Repeat the simulation.Do e s it still work?1Part III – Pipelined M ultiplication1. Add a new module to your project which will be a CoreGen-generated 8x8–> 16 signed multiplier (MathFunctions–>Multipliers–>Multiplier v10.1). Select “Use Mults” for the Multiplier Construction. Onthe la st dialog page, set the number of pipeline stages to 3. Leave all other settings at their suggesteddefaults.2. Following the .VHO file generated by CoreGen, add the following COMPONENT declaration to your“la14.vhd” file between the ARCHITECTURE and BEGIN lines:component la14multiplier -- change component name to whatever you called itport (clk: IN std_logic;a: IN std_logic_VECTOR(7 downto 0);b: IN std_logic_VECTOR(7 downto 0);p: OUT std_logic_VECTOR(15 downto 0));end component;3. Again following the .VHO file, instantiate this component in your design, replacing the behaviora ldescription “X <= A*B”:U1 : la14multiplier -- change component name to whatever you called itport map (clk => clk,a => a,b => b,p => x);You w ill also have to:• add a CLK input signal to your design• change the types of the A, B, and X buses to be STD_LOGIC_VECTOR4. Synthesize and Implement your project. Note the LUT usage and maximum C L K-to-X propagationdelay. Is this faster than a purely-combinational multiplier?5. Create a new Testbench Waveform simulation file for Behavioral Simulation. At the first clock edge,set A=0x23 and B=0 x34. At the second clock edge set A=0xFF. Run the simulation and note thepipelining effects in the output. When is the actual result available (remember you were to set thenumber of pipeline stages to 3)? Is it corre