Back of Envelope Inspection Method Assume then Validate Method Ideal Operational Amplifier Op Amp inverting terminal noninverting terminal v1 v2 1 vi i1 i3 i2 3 2 The nonlinear relationship F depends only on v3 F vi vi v 2 v1 v3 E sat F vi is defined by v 3 E sat i f v i 0 v 3 E sat if v i 0 E sat v 3 E sat output terminal 4 i1 0 i2 0 v3 Esat is called the saturation if v i 0 voltage Typically E sat 15 V vi v2 v1 0 v3 Esat sgn vi E sat Linear Region Operating Region op amp Circuit Model vi 0 ib b c 0 Validating Inequality Region Region vo a ia c vi 0 E sat d op amp Equation Saturation a ia a ia Saturation ib b vo d c vi 0 E sat ib b vo d ia 0 ia 0 ia 0 ib 0 ib 0 ib 0 vi 0 v o E sa t v o E sat E sa t v o E sa t vi 0 vi 0 OP AMP in Linear Region ea ia 0 a i0 vi 0 eb b ib 0 OP AMP Element Laws Linear Region ia 0 ib 0 vi eb ea 0 v0 ea a ia 0 b i0 0 vi 0 eb ib 0 Remark i0 and v0 can assume any value determined by the external circuit v0 Simple Op Amp Circuit Analysis 3 Common Steps Step 1 Assume Op Amp Regime Replace Op Amp by circuit model for the assumed regime Step 2 Solve the resulting linear resistive circuit 3 typical problems find operating point derive and sketch DP plot derive and sketch TC plot Step 3 Derive the dynamic range of the Op Amp s assumed operating regime Derive the op amp regime validation variable vi for linear regime and vo for saturation regimes and apply the regime validation inequality 5 Analysis Steps within each Regime 1 Express the current of each resistor in terms of its node to datum voltages via Ohms law and KVL 2 Apply KCL to all nodes except the ground datum node and the op amp output node 3 Solve for the desired variable 4 Solve for the op amp regime validation variable vi for linear regime vi for saturation regimes as a function of the driving point voltage or current 5 Apply the appropriate regime validation inequality and calculate the dynamic range in terms of the driving point voltage v i e va v vb or in terms of the driving point current i i e ia i ib Find Output Voltage vo for Op amp operating in the Linear Region R2 10 K R1 5 K 10 vo Replace Op amp by Model in Linear Regime R2 10 K R1 5 K 0 10 vo R2 10 K R1 5 K vi vo vo Esat R2 vo vi R1 R1 Esat R2 R1 Esat R2 0 Esat vi Validation Find a dynamic range of the driving point voltage vi where op amp is operating in the assumed linear regime Validation Inequality Esat v0 Esat since R2 vo vi R1 Esat R2 vi Esat R1 R1 Right inequality vi Esat R2 Left inequality R1 vi Esat R2 Op amp circuit realization of linear controlled sources i1 0 i2 g v1 1 R g dynamic range v2 Esat v1 v2 Esat VCCS v1 0 v2 r i1 r i2 i1 A v 1 R R R i1 dynamic range E E sa t i1 sa t R R v 2 i2 A v1 v2 CCVS i1 0 v2 v1 1 R2 R1 i1 dynamic range R1 R1 E v sat 1 Esat R1 R2 R1 R2 VCVS v1 0 i2 i1 R1 1 R2 dynamic range v 2 E sat v 2 E sat i 1 R R 1 1 CCCS R2 A v1 i2 v2 R1 i2 i1 v 1 R1 A R2 v2 DP Plot of an op amp VCCS Circuit i 1 v 3 2 E i 1 E R vo R Linear Region E E sat 0 E E sat v 4 Linear Region i 1 2 v 3 i 0 v 0 i iR i 0 R vR R iR E 4 Step 1 Derive an equation relating v and i across terminals 1 3 1 DP plot in the linear region vo i iR vR E R iR Substitute 2 into 1 i E E 0i v R R 1 2 3 This equation describes the Norton equivalent circuit across terminals 1 3 i G eq v isc Geq 0 isc E R 4 i i 0 1 2 v 0 i iR i 0 E R vR R iR 4 1 v 3 vo Step 2 Validation Esat vo Esat To test the above condition for the op amp to be operating in the linear region we must derive an equation relating vo and v Apply KVL around closed node sequence 1 3 4 1 2 v vo E vi 0 5 vo E v 6 Hence Esat vo Esat implies E Esat v E Esat 7 i 1 2 E v 3 E R Linear Region E sat vo R 4 i 1 R 1 E E sat 0 E E sat v Saturation Region i 1 i 0 1 v Step 1 Derive an equation relating v and i 3 DP plot in the saturation region 2 vi 0 E iR i 0 E R vR R iR 4 sa t vo Apply KVL around closed node sequence 1 2 4 3 1 v Ri Esat 8 Step 2 Validation vi 0 To test the above condition for the op amp to be operating in the saturation region we must derive an equation relating vi and v Apply KVL around closed node sequence 1 2 4 1 3 v vi E Esat 0 vi v E Esat 9 Hence vi 0 implies v E Esat 10 i 1 2 E v 3 Linear Region E R R E sat vo R 4 i 1 R 1 E E sat 0 E E sat 1 v Saturation Region i 1 i 0 1 v Step 1 Derive an equation relating v and i 3 2 vi 0 DP plot in the saturation region E iR i 0 E R vR R iR 4 sa t vo Apply KVL around closed node sequence 1 2 4 3 1 v Ri Esat 11 Step 2 Validation vi 0 To test the above condition for the op amp to be operating in the saturation region we must derive an equation relating vi and v Apply KVL around closed node sequence 1 2 4 3 1 v vi E Esat 0 vi v E Esat 12 Hence vi 0 implies v E Esat 13 Remark The above op amp circuit functions as a VCCS defined by i1 0 14 i2 G21 v1 Upon defining v1 E i1 0 15 i2 i G21 E R It is valid over the voltage range E Esat v2 E Esat 16
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