Berkeley
ELENG 100 -
Pentium II with L2 Cache
School name
University of California, Berkeley
Pages 6
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Pentium II with L2 Cache Pentium II Block Diagram To From Bus Bus Unit Memory Manager A L U Data Cache Integer Branch Predictor Code Cache Integer Floating point Prefetch Control Unit Decode Circuit Complexity vs Time Assembler Code Example MouPos MouPos PROC FAR Value DWORD PUSH ES PUSH DI PUSH CX PUSH DX LES DI Value MOV AX 3h INT 33h MOV AX CX STOSW MOV AX DX STOSW POP DX POP CX POP DI POP ES RET ENDP Out Of Order Processing R3 R4 R7 R5 R6 R7 R7 memory 1000 R7 memory 1001 Is Replaced with R3 R4 R7 R7 memory 1000 R5 R6 R17 R17 memory 1001 Embedded Controllers Typical Cost 100 Ports RS 232 parallel direct I O FORTH Programming language PROM contains program Interrupt vs Polling Object Oriented programming
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