Slide 1WHAT IS THE ORIGIN OF GATE DELAY?INVERTER VOLTAGE WAVEFORMS (TIME FUNCTIONS)GATE DELAY (PROPAGATION DELAY)EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEEDWHAT DETERMINES GATE DELAY?Modern Field Effect Transistor (FET)Slide 8Slide 9Slide 10CMOS Inverter Power Dissipation due to Direct-Path CurrentSlide 12Slide 13Slide 14Calculating the Propagation DelayCalculating the Propagation Delay (cont’d)Output Capacitance of a Logic GateReminder: Fan-OutMinimizing Propagation DelayMOSFETTransistor Sizing for PerformanceSlide 22CMOS NAND GateCMOS NOR GateSlide 25Slide 26ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEWENERGY AND POWER IN CHARGINGENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORSENERGY IN DISCHARGING CAPACITORSCMOS Power ConsumptionPOWER DISSIPATION in DIGITAL CIRCUITSLOGIC POWER DISSIPATION EXAMPLELOGIC POWER DISSIPATION with power mitigationLow-Power Design TechniquesEE42/100, Spring 2006 Week 14a, Prof. White 1Week 14aPropagation delay of logic gates CMOS (complementary MOS) logic gatesPull-down and pull-upThe basic CMOS inverterCurrent flow and power dissipation in CMOS circuitsEquation for power dissipated in N logic circuits clocked at frequency fEE42/100, Spring 2006 Week 14a, Prof. White 2WHAT IS THE ORIGIN OF GATE DELAY?Logic gates are electronic circuits that process electrical signalsMost common signal for logic variable: voltageNote that the specific voltage range for 0 or 1 depends on “logic family,” and in general decreases with succeeding logic generationsSpecific voltage ranges correspond to “0” or “1”Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing3210VoltsRange “0”Range “1”“Gray area” . . . not allowedEE42/100, Spring 2006 Week 14a, Prof. White 3INVERTER VOLTAGE WAVEFORMS (TIME FUNCTIONS)Inverter input is vIN(t), output is vOUT(t)Inverter inside a large system)t(vIN)t(vOUTtVin(t)EE42/100, Spring 2006 Week 14a, Prof. White 4ApproximationDGATE DELAY (PROPAGATION DELAY)Define as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V.Inverters are designed so that the gate delay is symmetrical (rise and fall)Vin(t)t1.5Vout(t)t1.5DDEE42/100, Spring 2006 Week 14a, Prof. White 5EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEEDComputer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculationsImplication: if clock frequency = 500 MHz clock period = (5108 s1)1Period = 2 10 9s = 2 ns (nanoseconds)Gate delay must be D = (1/35) Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3 108 m/sDistance traveled in 57 ps is:c X D = (3x108m/s)(57x10-12s) = 17 x 10-4 m = 1.7cmEE42/100, Spring 2006 Week 14a, Prof. White 6WHAT DETERMINES GATE DELAY?)t(vIN)t(vOUTThe delay is mostly simply the charging of the capacitors at internal nodes.Logic gates consist of just “CMOS” transistor circuits (CMOS =complementary metal-oxide-semiconductor = NMOS and PMOS FETs together).Let’s recall the FETEE42/100, Spring 2006 Week 14a, Prof. White 7Modern Field Effect Transistor (FET)•An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying “gate” electrode), to modulate the conductance of the semiconductorModulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrodeN-channel metal-oxide- semiconductor field-effect transistor (NMOSFET)EE42/100, Spring 2006 Week 14a, Prof. White 8Pull-Down and Pull-Up Devices•In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD.–An NMOSFET functions as a pull-down device when it is turned on (gate voltage = VDD)–A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND)F(A1, A2, …, AN)PMOSFETs onlyNMOSFETs only……Pull-upnetworkPull-downnetworkVDDA1A2ANA1A2ANinput signalsEE42/100, Spring 2006 Week 14a, Prof. White 9Controlled Switch ModelNow lets combine these switches to make an inverter.-Type N controlled switch” means switch is closed if input is high. (VG > VS)Type P controlled switch” means switch is closed if input is low. (VG < VS)OutputSInputRP-++-+-GInputOutputRN++-+-GSEE42/100, Spring 2006 Week 14a, Prof. White 10The CMOS Inverter: Current Flow during SwitchingVINVOUTVDDVDD00N: offP: linN: linP: offN: linP: satN: satP: linN: satP: satAB D ECiiiSDGGSDVDDVOUTVINEE42/100, Spring 2006 Week 14a, Prof. White 11CMOS Inverter Power Dissipation due to Direct-Path CurrentVDD-VTVTtimevIN:i:IpeakVDD00iSDGGSDVDDvOUTvINpeakDDscdpIVtE Energy consumed per switching period:tscNote: once the CMOS circuit reaches a steady state there’s no more current flow and hence no more power dissipation!EE42/100, Spring 2006 Week 14a, Prof. White 12Controlled Switch Model of InverterSo if VIN is 2V then SN is closed and SP is open. Hence VOUT is zero.InputOutputRN-+SP is closed if VIN < VDDRP-++-+-VDD = 2VVSS = 0VSNSPSN is closed if VIN > VSSVINVOUTBut if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V.EE42/100, Spring 2006 Week 14a, Prof. White 13Controlled Switch Model of InverterIF VIN is 2V then SN is closed and SP is open. Hence VOUT is zero (but driven through resistance RN).RN+--VDD = 2VVSS = 0VVIN =2V VOUTBut if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V (but driven through resistance RP).+--VDD = 2VVSS = 0VVIN =0V RPVOUTEE42/100, Spring 2006 Week 14a, Prof. White 14VIN jumps from 0V to 2VControlled Switch Model of Inverter – load capacitor charging and discharging takes timeIF there is a capacitance at the output node (there always is) then VOUT responds to a change in VIN with our usual exponential form.VOUTtVIN jumps from 2V to 0VRN+--VDD = 2VVSS = 0VVIN =2V VOUT+--VDD = 2VVSS = 0VVIN =0V RPVOUTEE42/100, Spring 2006 Week 14a, Prof. White 15Model the MOSFET in the ON state as a resistive switch:Case 1: Vout changing from High to Low (input signal changed from Low to High) NMOSFET(s) connect Vout to GNDtpHL= 0.69RnCL Calculating the Propagation DelayVDDPull-down network is modeled as a resistorPull-up network is modeled as an open switchCL+vOUTvIN = VDDRnEE42/100, Spring 2006 Week 14a, Prof. White 16Calculating
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