1Chapter 16NMOS InverterChapter 16.1¾ In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology of choice.¾ Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration.¾ The small transistor size and low power dissipationof CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.MOSFET Digital CircuitsNMOS Inverter • For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.• Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. MOSFET Digital Circuits2n-channel MOSFET n-channel MOSFETn-Channel MOSFET Formulas Transition points Saturation region Nonsaturation regionÆÆChap.3NMOS Inverter • For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.• Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.3++VGS=NMOS Inverter ¾ As the input voltage increases (VGS), the drain to source voltage (VDS) decreases and the transistor inter into the nonsaturation region.¾ If VI <VTN, the transistor is in cutoff and iD= 0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS=VDD=VDSVI <VNTTransistor offVI >VNTTransistor on¾ If VI >VTN, the transistor is on and initially is biased in saturation region, since VDS< VGS-VTN.++VGS==VDD=VDSCut-offNMOS Inverter with Resister Load¾ If VI <VTN, the transistor is in cutoff and iD= 0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS¾ As the input is increased slightly above the VTN, the transistor turns on and is in the saturation region. ++VGS==VDSSaturation RegionNMOS Inverter with Resister LoadSaturation regionTransition RegionNMOS Inverter with Resister Load¾ The Q-point of the transistor moves up the load line. ¾ As the input voltage is further increases and voltage drop across the RDbecome sufficient to reduce the VDSsuch that TNGSDSVVV−≤++VGS==VDSAt the transition point,Saturation region4¾ As the input voltage becomes greater than VIt, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region.Nonsaturation RegionSaturation region++VGS==VDSNonsaturation regionNMOS Inverter with Resister LoadVGS= vIVDS= vONMOS Inverter with Resister Load++VGS==VDSThe sharpness of the transition region increases with increasing load resistance.The minimum output voltage, or the logic 0level, for a high input decreases with increasing load resistance.Input-Output RelationshipSummary of NMOS inverter with Resister LoadCurrent-Voltage RelationshipNonsaturation RegionSaturation RegionTransition RegionÆExampleFor the NMOS inverter shown in Fig. VDD= 3V. Assume transistor parameters of K’n= 60 µA/v2, W/L = 5, and VTN= 0.5 V. (a) Find the value of RDsuch that vo= 0.1 V when vI= 3 V. (b) Using the results of part (a) determine the transition point for the driver transistor5n-Channel MOSFET connected as saturated load device• An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS inverter.• Since the gate and drain of the transistor are connected, we haveVGS=VDSWhen VGS=VDS>VTN, a non zero drain current is induced in the transistor and thus the transistor operates in saturation only. And following condition is satisfied.VDS>(VGS-VTN) VDS(sat)= (VDS-VTN) because VGS=VDS or VDS(sat)= (VGS-VTN)In the saturation region the drain current is iD=Kn(VGS-VTN)2= Kn(VDS-VTN)2The iDversus vDScharacteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.NMOS Inverter with Enhancement Load¾ This basic inverter consist of two enhancement-only NMOS transistors¾ Much more practical than the resisterloaded inverter, because theresistors are thousand of times largersize than a MOSFET.NMOS Inverter with Enhancement Load¾ An n-channel enhancement-mode MOSFET with gate connected to the drain can be used as a load device.Device acts as a Nonlinear resistor !!!Nonlinear resistor !!!6NMOS Inverter with Enhancement LoadWhen vI< VTNDNMOS Inverter with Enhancement LoadWhen vI> VTNDJust greater thanNMOS Inverter with Enhancement Load NMOS Inverter with Enhancement LoadWhen vI> VIt7NMOS Inverter with Enhancement Load NMOS Inverter with Resister Load++VGS==VDSThe sharpness of the transition region increases with increasing load resistance.The minimum output voltage, or the logic 0level, for a high input decreases with increasing load resistance.Input-Output Relationshipc.f.NMOS Inverter with Enhancement LoadLimitation of Enhancement Load inverterExampleP10148Limitation of Enhancement Load inverterExample 16.3P1014ExampleThe enhancement-load NMOS inverter shown in Fig. is biased at VDD= 3 V. The transistor parameters are VTND= VTNL= 0.4 V, k’n= 60 mA/V2, (W/L)D= 16 and (W/L)L= 2. (a) Find vowhen (i) vI= 0, (ii) vI= 2.6, (b) Calculate the power dissipated in the inverter when vI= 2.6 V.9NMOS Inverter with Depletion Load¾ This is an alternate form of the NMOS inverter that uses an depletion-mode MOSFET load device with gate and source terminal connected.¾ This inverter has the advantage of VO= VDD, as well as more abrupt transition region even though the W/L ratio for the output MOSFET is small.Depletion mode : Channel exists even with zero gate voltage.A negative voltage must be applied to the gate to turn the device off.Threshold voltage is always negative.N-Channel Depletion-Mode MOSFET• In n- channel depletion mode MOSFET, an n-channel region or inversion layer exists under the gate oxide layer even at zero gate voltage and hence term depletion mode.• A negative voltage must be applied to the gate to turn thedevice off.•Thethreshold voltageis alwaysnegativefor this kind of device.NMOS Inverter with Depletion LoadGate and source are connected,Since the threshold voltage of load transistor is negative.LoadNMOS Inverter with Depletion Load10NMOS Inverter with Depletion Load (cont.)Case I: when VI<VTND(drive is cutoff): No drain current conduct in either transistor. That means the load transistor must be in the linear region of the operation and the output current can