USA EE 334 - Chapter 3 Field-Effect Transistors (22 pages)

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Chapter 3 Field-Effect Transistors



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Chapter Goals Chapter 3 Field Effect Transistors Describe operation of MOSFETs and JFETs Define MOSFET characteristics in operation regions of cutoff triode and saturation Discuss mathematical models for i v characteristics of MOSFETs and JFETs Introduce graphical representations for output and transfer characteristic descriptions of electronic devices Define and contrast characteristics of enhancement mode and depletion mode MOFETs Define symbols to represent MOSFETs in circuit schematics Investigate circuits that bias transistors into different operating regions MOSFET and JFET DC circuit analysis Explore MOSFET modeling in SPICE Types of Field Effect Transistors MOSFET Metal Oxide Semiconductor Field Effect Transistor Primary component in high density VLSI chips such as memories and microprocessors JFET Junction Field Effect Transistor Finds application especially in analog and RF circuit design 1 The MOS Transistor Polysilicon Aluminum The NMOS Transistor Cross Section n areas have been doped with donor ions arsenic of concentration ND electrons are the majority carriers Gate oxide Polysilicon W Gate Source Drain Field Oxide n n SiO2 L p substrate p stopper Bulk Body p areas have been doped with acceptor ions boron of concentration NA holes are the majority carriers MOS Capacitor Structure First electrode Gate Consists of low resistivity material such as highly doped polycrystalline silicon aluminum or tungsten Substrate Conditions for Different Biases Accumulation VG VTN Depletion VG VTN Second electrode Substrate or Body n or ptype semiconductor Dielectric Silicon dioxide stable high quality electrical insulator between gate and substrate Inversion VG VTN 2 Low frequency C V Characteristics for MOS Capacitor on P type Substrate MOS capacitance is nonlinear function of voltage Total capacitance in any region dictated by the separation between capacitor plates Total capacitance modeled as series combination of fixed oxide capacitance and voltage dependent depletion layer capacitance NMOS Transistor Structure 4 device terminals Gate G Drain D Source S and Body B Source and drain regions form pn junctions with substrate vSB vDS and vGS always positive during normal operation vSB must always reverse bias the pn junctions 3 The Threshold Voltage VT VT0 2 F VSB 2 F where VT0 is the threshold voltage at VSB 0 and is mostly a function of the manufacturing process Difference in work function between gate and substrate material oxide thickness Fermi voltage charge of impurities trapped at the surface dosage of implanted ions etc VSB is the source bulk voltage F Tln NA ni is the Fermi potential T kT q 26mV at 300K is the thermal voltage NA is the acceptor ion concentration ni 1 5x1010 cm 3 at 300K is the intrinsic carrier concentration in pure silicon 2q siNA Cox is the body effect coefficient impact of changes in VSB si 1 053x10 10F m is the permittivity of silicon Cox ox tox is the gate oxide capacitance with ox 3 5x10 11F m The Body Effect 0 9 0 85 z VSB is the substrate bias voltage normally positive for n channel devices with the body tied to ground 0 8 VT V 0 75 0 7 0 65 0 6 z A negative bias causes VT to increase from 0 45V to 0 85V 0 55 0 5 0 45 0 4 2 5 2 1 5 VBS V 1 0 5 0 4 Concept of Asymmetric Channel Transistor in Saturation Mode Assuming VGS VT VGS S VDS G D n It is to be noted that the VDS measured relative to the source increases from 0 to VDS as we travel along the channel from source to drain This is because the voltage between the gate and points along the channel decreases from VGS at the source end to VGS VDS When VDS is increased to the value that reduces the voltage between the gate and channel at the drain end to Vt that is VDS VGS Vt or VDS sat VGS Vt VGS VDS Vt or VDS VGS VT ID n V V GS T Pinch off B The current remains constant saturates by vG 5 Channel Length Modulation Nonsaturation region As vDS increases above vDSAT the length of the depleted channel beyond pinch off point DL increases and actual L decreases Transition points iD increases slightly with vDS instead of being constant channel length modulation parameter Saturation region iD Kn W 2 L 2 v VTN 1 v DS GS v DS sat vGS VTN 6 Channel Length Modulation Key design parameter As vDS increases above vDSAT the length of the depleted channel beyond pinch off point DL increases and actual L decreases pCox iD increases slightly with vDS instead of being constant channel length modulation parameter Example 5 1 iD Kn W 2 L 2 v VTN 1 v DS GS P252 7 Example 5 2 P256 Key design parameter 8 Depletion Mode MOSFETS n Channel MOSFET NMOS transistors with VTN 0 Ion implantation process is used to form a built in n type channel in the device to connect source and drain by a resistive channel Non zero drain current for vGS 0 negative vGS required to turn device off 9 Problem solving Technique MOSFET DC Analysis STep1 Requires knowing the bias condition of the transistor such as cutoff or saturation or nonsaturation Step2 If the bias condition is not obvious one must guess the bias condition before analyzing the circuit Step3 How can we Guess i Assume that the transistor is biased in the saturation region which implies that ID 0 and VDS VDS sat VGS VTN If all the above conditions are satisfied analyze the circuit using the saturation current voltage relations ii If VGS VTN then transistor is probably in cutoff mode iii If VDS VDS sat the transistor is likely biased in nonsaturation region analyze the circuit using nonsaturation current voltage relations MOSFET Circuit Symbols g and i are the most commonly used symbols in VLSI logic design MOS devices are symmetric In NMOS n region at higher voltage is the drain In PMOS p region at lower voltage is the drain 10 Channel Length Modulation As vDS increases above vDS sat the depleted channel length beyond pinch off point L increases and actual L decreases iD increases slightly with vDS instead of being constant Summary of the MOSFET Current Voltage relationship MOSFET DC Analysis The DC circuit analysis is an important part of the design of an amplifier Table 5 1 11 Bias Analysis Approach Assume a region of operation generally the saturation region Use circuit analysis to find VGS Use VGS to calculate ID and ID to find VDS Check validity of operation region assumptions Change assumptions and analyze again if required NOTE An enhancement mode device with VDS VGS is always in saturation Four Resistor and Two Resistor Biasing Provide excellent bias for transistors in discrete


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