1MOS Digital CircuitsChapter 16• In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology choice.• Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration.• The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.NMOS Inverter • For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.• Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. NMOS Inverter•If VI <VNT, the transistor is in cutoff and iD=0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS•If VI >VNT, the transistor is on and initially is biased in saturation region, since •VDS >VGS-VTN.• As the input voltage increases (VGS) , the drain to source voltage (VDS) decreases and the transistor inter into the non saturation region.++VGS=VRD=VDD=VDSNMOS Inverter Transfer Characteristics with load resister (Saturation Region)++VGS=VRD=VDD=VDSVGS=VRD=VDD=VDSAs the input is increased slightly above the VTN, the transistor turns on and is in the saturation region. The output voltage is thenvo= VDD –iDRD(16.6 )where the drain current is given byiD= Kn(VGS-VTN)2= Kn(Vi-VTN)2( 16.7)By substituting the value of IDfrom Eq. 16.7 we get ,VO= VDD-KnRD(VI-VTN)2(16.8) which relates the output and input voltages as long as the transistor is biased in the saturation region.NMOS Inverter Transfer Characteristics with load resister (transition Region)• As the input voltage is further increases and voltage drop across the RDbecome sufficient to reduce the drain to source voltage such that VDS≤VGS-VTN.the Q-point of the transistor moves up the load line. At the transition point, we havevot= VIt-VTN16.9where Vo, and VI, are the drain-to-source and gate-to-source voltages, respectively, at the transition point. By substituting Equation (16.9) into (16.8), the input voltage at the transition point can be determined as,KnRD(VIt-VTN)2+ (VIt-VTN) - VDD= 0++VGS=VRD=VDD=VDSVGS=VRD=VDD=VDSNMOS Inverter Transfer Characteristics with load resister (Nonsaturation Region)• As the input voltage becomes greater than VIt, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is theniD= Kn[2(VGS-VTN)VDS–VDS2]= Kn[2(vI-VTN)VO– Vo2] (16.11)The output voltage is then determined by vo = VDD–iDRDSubstitute the value of IDfrom above equation we get the output voltage relation when the transistor is biased in nonsaturation region.VO= VDD–KnRD[2(vl-VTN)vo -vo2]++VGS=VRD=VDD=VDSVGS=VRD=VDD=VDS2++VGS=VRD=VDD=VDSVGS=VRD=VDD=VDSIt should be be noted that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance. Summary of NMOS inverter C-V relationship with the resister load• Saturation region• Transition regioniD= Kn(VGS-VTN)2= Kn(Vi-VTN)2VO= VDD-KnRD(VI-VTN)2 vot= VIt-VTNKnRD(VIt-VTN)2+ (VIt-VTN) -VDDNonsaturation region= Kn[2(vI-VTN)VO– Vo2] iDVO= VDD–KnRD[2(vl-VTN)vo - vo2] ++VGS=VRD=VDD=VDSVGS=VRD=VDD=VDSNMOS Inverter with Enhancement Load• This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the resister loaded inverter, which is thousand of times larger than a MOSFET.n-Channel MOSFET connected as saturated load device• An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS inverter.• Since the gate and drain of the transistor are connected, we haveVGS=VDSWhen VGS=VDS>VTN, a non zero drain current is induced in the transistor and thus the transistor operates in saturation only. And following condition is satisfied.VDS>(VGS-VTN) VDS(sat)= (VDS-VTN) because VGS=VDS or VDS(sat)= (VGS-VTN)In the saturation region the drain current is iD=Kn(VGS-VTN)2= Kn(VDS-VTN)2The iDversus vDScharacteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.NMOS Inverter with Enhancement Load/SaturatedIn the saturation region the loaddrain current is iDL=KL(VGSL-VTNL)2= KL(VDSL-VTNL)2For VGSD<VTN ( driver transistor )transistor is in cutoff mode and does not conduct drain current0= iDL=KL(VGSL-VTNL)2= KL(VDSL-VTNL)2VGSL=VTNL or VDSL=VTNLAs a result the output high voltage VO is degraded by the threshold voltage or VO,, max= VOH=VDD-VTNLNMOS inverter with Enhancement Load/Saturated (Cont.)• As the VI=>VTND A non zero drain current is induced in the transistor and thus the drive transistor operates in saturation only. As shown in the figure the following condition is satisfiediDD=iDL orKD(VGSD-VTND)2= KL(VGSL-VTNL)2Substituting VGSD=VIand VGSL=VDD-VO yieldsKD(VI-VTND)2= KL(VDD- VO- VTNL)2Solving for VOgivesVO= VDD-VTNL-KD/KL(VI-VTND)3NMOS inverter with Enhancement Load/Saturated (driver at the transition point)• As the input voltage (VGS) further increases, the drive Q-point moves up and switch into the transition region., we haveVDSD(sat)= VGSD-VTNDIn terms of input/output transition voltagesor VOt=VIt-VTNDSubstituting above Equation into following equationVO= VDD-VTNL-KD/KL(VI-VTND)we find the input voltage at the transition point, which isVIt= [VDDVTNL+VTND(1+ KD/KL)]/(1+ KD/KL)NMOS Inverter with Enhancement Load/Saturated (driver at the non saturation region))As the input voltage becomes greater than VItthe driver transistor Q- point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD= iDL, we now haveKD[2(VGSD-VTND)VDSD-VDSD2] = KL(VDSL-VTNL)2Substituting VGSD=VI and VDSD=VOand VDSL= VDD-VOwe getKD[2(vl-VTND) Vo-VO2] = KL(VDD- VO-VTNL)2The ratio KDIKLis the aspect ratio and is related to the width-to-length parameters of the driver and load transistors.The slope of the VTC curves in the saturation region is known as inverter gain and is given bydVo/dVI= - KD/KLIf the inverter gain is greater then unity, the inverter logic gate is belonged to restoring logic family. Limitation of NMOS inverterExample 16.3Limitation of