1Bipolar junction Transistor characteristicsNMOS Inverter • For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.• Once the operation and characterization of the inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.2++VGS=VRD=VDD=VDSVGS=VRD=VDD=VDSIt should be be noted that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance. NMOS Inverter with Enhancement Load• This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the resister loaded inverter, which is thousand of times larger than a MOSFET.NMOS Inverter with Enhancement LoadVO,, max= VOH=VDD-VTNLFor good logic 0 required high aspect ratio!Limitation of NMOS inverterExample 16.33NMOS Inverter with Depletion Load• This is an alternate form of the NMOS inverter that uses an enhancement-depletion MOSFET load device with gate and source terminal connected.• This inverter has the advantage of VO= VDD, as well as more abrupt VTC transition region even though the W/L ratio for the output MOSFET is small.•The term depletion modemeans that a channel exists even with zero gate voltage.VT Characteristics of NMOS Inverter with Depletion LoadThe Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small.41160µW825µW200µWAll the examples and home work problems related to power dissipation are important!Transient Analysis of NMOS inverters• The source of capacitance CT2and CT3are the transistor input capacitances and parasitic capacitancesdue to interconnect lines between the inverter stages.• The constant current over a wide range of VDSprovided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter configurations.The rate at Transient Analysis of NMOS inverters (cont.)• The fall time relatively short, because the load capacitor discharges through the large drive transistor.• The raise time is longer because the load capacitor is charged by the current through the smaller load transistor.(W/L)L=1(W/L)D=4F-0.5pFConcept of effective width to length ratiosFor the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased..Parallel combinationSeries combinationNAND gate for more than three inputs is not attractive???5NMOS NOR gate: Special case when all inputs are at logic 1When A=B=logic 1Both driver transistors are switched into nonsaturation regionand load transistor is biased in saturation region. We haveiDL=iDA+iDBBy substituting the values of current equation we can write as,KL(VGSL-VTNL)2 = KDA[2(VGSA-VTNA)VDSA-VDSA2] + KDB[2(VGSB-VTNB)VDSB-VDSB2] Suppose two driver transister are identical, which implies that,KDA=KDB=KDVTNA=VTNB=VTNDAs we know VGSL=0Also from figure VGSA=VGSB=VDDVDSA=VDSB=V0By substituting all these parameters we can write above equation as,(-VTNL)2= 2(KD/KL)[2(VDD-VTND)V0-VO2)Conclusion: The above equation suggested that when the both the driver are in conducting mode, the effective aspect ratio of the NOR gate is double. This further suggested that output voltage becomes slightly smaller when both inputs are high. Because higher the aspect ratio lower the output.When all the inputs are high: design consideration!!MDCVGSCiDCMDCCThree input NOR gate design considerationsThree input NANDgate designconsiderations• At present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications.• The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive.• Although the processing is more complicated for CMOS circuits than for NMOS circuits. • However, the advantages of CMOS digital circuits over NMOS circuits justify their use. CMOS: the most abundant electronic devices on earthFull rail-to-rail swing ⇒ high noise marginszLogic levels not dependent upon the relative device sizes ⇒transistors can be minimum size ⇒ ratio lessAlways a path to Vddor GND in steady state ⇒ low output impedance (output resistance in kΩ range) ⇒large fan-out.Extremely high input resistance (gate of MOS transistor is near perfect insulator) ⇒ nearly zero steady-state input currentNo direct path steady-state between power and ground ⇒ no static power dissipationPropagation delay function of load capacitance and resistance of transistorsCMOS properties6CMOS Inverter: Steady State ResponseVDDRnVout= 0Vin= VDDVDDRpVout= 1Vin= 0VOL= 0VOH= VDDNMOS offPMOS in non satNMOS in satPMOS in non satNMOS in satPMOS in satNMOS in non satPMOS in satNMOS in nonsatPMOS offCMOS inverter design consideration• The CMOS inverter usually design to have, (i) VTN=|VTP|(ii) K´n/2(W/L)=K´p/2 (W/L)But K´n>K´p(because µn>µp)How equation (ii) can be satisfied?This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.Symmetrical properties of the CMOS inverter7CMOS inverter VTCVCCVCCVinVoutkp=knkp=5knkp=0.2kn• Increase W of PMOSkpincreasesVTC moves to right• Increase W of NMOSknincreasesVTC moves to left• For VTH= Vcc/2kn= kpWn≈ 2Wp8Effects of VItadjustment• Result from changing kp/knratio:– Inverter threshold VIt≠ Vcc/2– Rise and fall delays unequal– Noise margins not equal• Reasons for changing inverter threshold– Want a faster delay for one type of transition (rise/fall)– Remove noise from input signal: increase one noise margin at expense of the otherPower Dissipation• Although there isn't power dissipation in the CMOS inverter when the output is either at logic 0 or 1. However, during switching of the CMOS inverter from low logic 0 to logic 1, current flows and power is dissipated.• Usually CMOS inverter and logic circuit are used to drive other MOS devices by connecting a capacitor across the output of a