1Chapter 16CMOS InverterChapter 16.3p-Channel MOSFETppnpn¾ In p- channel enhancement device. A negative gate-to- source voltage must be applied to create the inversion layer, or channel region, of holes that, “connect” the source and drain regions.¾ The threshold voltage VTPfor p-channel enhancement-mode device is always negative and positive for depletion-mode PMOS.p-Channel MOSFETCross-section of p-channel enhancement mode MOSFET2Complementary MOSCMOSThe most abundant devices on earth¾ Although the processing is more complicated for CMOS circuits than for NMOS circuits, CMOS has replaced NMOS at all level of integration, in both analog and digital applications.¾ The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits.CMOS PropertiesFull rail-to-rail swing Îhigh noise marginszLogic levels not dependent upon the relative device sizes transistors can be minimum size ratio lessAlways a path to VDDor GND in steady state Îlow output impedance (output resistance in kΩrange) large fan-out.Extremely high input resistance(gate of MOS transistor is near perfect insulator) nearly zero steady-state input currentNo direct path steady-state between power and ground no static power dissipationPropagation delay functionof load capacitance and resistance of transistorsÎÎÎÎξ In the fabrication process, a separate p-well region is formed within the starting n-substrate.¾ The n- channel MOSFET is fabricated in the p-well region and p- channel MOSFET is fabricated in the n-substrate.CMOS InverterSteady State ResponseVDDRnVOut= 0VIn= VDDVDDRpVOut= VDDVIn= 0CMOS InverterDDOHOLVVV==0PMOSNMOSPMOSNMOS34Voltage Transfer CurveCMOS Inverter Load Lines00.511.522.50 0.5 1 1.5 2 2.5IDN(A)Vout(V)X10-4Vin= 1.0VVin= 1.5VVin= 2.0VVin= 2.5V0.25um, W/Ln= 1.5, W/Lp= 4.5, VDD= 2.5V, VTn= 0.4V, VTp= -0.4VVin= 0VVin= 0.5VVin= 1.0VVin= 1.5VVin= 0.5VVin= 2.0VVin=1.0VPMOS NMOSVin=0VVin=0.5VVin=2.5VVin=2.0VVin=1.5VIDP(A)NMOS offPMOS in non satNMOS in satPMOS in non satNMOS in satPMOS in satNMOS in non satPMOS in satNMOS in nonsatPMOS offvSDPis smallvIand vOrelationship as long as NMOS: saturation, PMOS: nonsaturation5from below graphvOPtorfrom above graphvONtvItBCNMOS: nonsaturationPMOS: offNMOS: nonsaturationPMOS: saturationNMOS: saturationPMOS: saturationNMOS: saturationPMOS: nonsaturationNMOS: offPMOS: nonsaturation6Example 16.9p1041vItvOPtvONtFor VDD=5VExample 16.9p1041vItvOPtvONtvOPtvONtvItVDD=5VVDD=10V¾ The transistor KNis also known as “pull down” device because it is pulling the output voltage down towards ground.¾ The transistor KPis known as the “pull up” device because it is pulling the output voltage up towards VDD. This property speed up the operation considerably.The static power dissipation during both extreme cases (logic 1 or 0) is almost zerobecause iDP= iDN= 0.1001VOutVIn¾ CMOS inverter: series combination of PMOS and NMOS¾ To form the input, gates of the two MOSFET are connected.¾ To form the output, the drains are connected together.(ideal case)Ideally, the power dissipation of the CMOS inverter is zero.Practical deviceCMOS inverter (∼ nW) NMOS inverter (∼mW)CMOS Inverter in either High or Low State7CMOS Inverter Design Consideration The CMOS inverter usually design to have, 9 This can achieved if width of the PMOS is made two or three times than that of the NMOS device. 9 This is very important in order to provide a symmetrical transition, results in wide noise margin.But (because µN>µP)(1)(2)TPTNVV ==LWkLWkPN''''PNkk >¾ How equation (2) can be satisfied ?NMOS: nonsaturationPMOS: offNMOS: nonsaturationPMOS: saturationNMOS: saturationPMOS: saturationNMOS: saturationPMOS: nonsaturationNMOS: offPMOS: nonsaturationSymmetrical Properties of the CMOS InvertervOPtvONt2DDItVV =8Example 16.29p1101(a)(i)Transition pointsVOPtVONt(ii)vItvOPtvONt=LWkKnN2'Example 16.29p1101(b)(i)(ii)Transition pointsVOPtVONt=LWkKPP2'Increase W of PMOS¼ kPincreases¼ VItmoves to rightVDDVDDVInVOutkp=5knkp=knkp=0.2knCMOS Inverter VTCIncrease W of NMOS¼ kNincreases¼ VItmoves to leftPNPNDDItWWkkVVfor≈=→=,2VIt Result from changing kP/kNratio:¾ Inverter threshold VIt≠ VDD/2¾ Rise and fall delays unequal¾ Noise margins not equalReasons for changing inverter threshold:¾ Want a faster delay for one type of transition (rise/fall)¾ Remove noise from input signal: increase one noise margin at expense of the otherCMOS Inverter VTCEffects of VItadjustment9Problem 16.31p1101(a)Problem 16.31p1101vItExample 16.31p1101(b)CMOS inverter currents¾ When the output of a CMOS inverter is either at a logic 1 or 0, the current in the circuit is zero.¾ When the input voltage is in the range both transistors are conducting and a current exists in the inverter.10CMOS inverter currents When NMOS transistor is biased in the saturation region¾ The current in the inverter is controlled by vGSNand the PMOS vSDPadjusts such that iDP = iDN .As long as NMOS transistor is biased in the saturation region thesquare root of the inverter current is linearfunction of the input voltage.CMOS inverter currents When PMOS transistor is biased in the saturation region¾ The current in the inverter is controlled by vSGPand the NMOS vDSN adjusts such that iDP = iDN .As long as PMOS transistor is biased in the saturation region the square root of the inverter current is linearfunction of the input voltage.NMOS: saturationPMOS: saturationNMOS: offPMOS: nonsaturationNMOS: saturationPMOS: nonsaturationCMOS inverter currentsNMOS: nonsaturationPMOS: offNMOS: nonsaturationPMOS: saturationProblem 16.33p1102(a)(b)11Power Dissipation¾ There is no power dissipation in the CMOS inverterwhen the output is either at logic 0 or 1. However, during switching of the CMOS inverter from low logic 0 to logic 1, current flowsand power is dissipated.¾ Usually CMOS inverter and logic circuit are used to drive other MOS devices by connecting a capacitor across the output of a CMOS inverter. This capacitor must be charged and discharged during the switching cycle.Triode RegionNMOS Transistor CapacitancesCox” = Gate-Channel capacitance per unit area(F/m2)CGC= Total gate channel capacitanceCGS= Gate-Source capacitanceCGD= Gate-Drain capacitanceCGSOand CGDO= overlap capacitances (F/m)Saturation RegionNMOS Transistor Capacitances¾ Drain is no longer connected to