1Chapter 5Field-Effect TransistorsChapter Goals• Describe operation of MOSFETs and JFETs.• Define MOSFET characteristics in operation regions of cutoff, triode and saturation.• Discuss mathematical models for i-vcharacteristics of MOSFETsand JFETs.• Introduce graphical representations for output and transfer characteristic descriptions of electronic devices.• Define and contrast characteristics of enhancement-mode and depletion-mode MOFETs.• Define symbols to represent MOSFETs in circuit schematics.• Investigate circuits that bias transistors into different operating regions.• MOSFET and JFET DC circuit analysis• Explore MOSFET modeling in SPICETypes of Field-Effect Transistors• MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor)– Primary component in high-density VLSI chips such as memories and microprocessors• JFET (Junction Field-Effect Transistor)– Finds application especially in analog and RF circuit design2The MOS TransistorPolysiliconAluminumThe NMOS Transistor Cross Sectionn areas have been doped with donor ions (arsenic) of concentration ND- electrons are the majority carriers p areas have been doped with acceptorions (boron) of concentration NA- holes are the majority carriers Gate oxiden+Source Drainp substrateBulk (Body)p+ stopperField-Oxide(SiO2)n+PolysiliconGateLWMOS Capacitor Structure• First electrode - Gate : Consists of low-resistivitymaterial such as highly-doped polycrystalline silicon,aluminum or tungsten• Second electrode -Substrate or Body: n-or p-type semiconductor•Dielectric- Silicon dioxide: stable high-quality electrical insulator between gate and substrate.Substrate Conditions for Different BiasesAccumulationVG << VTNDepletionVG < VTNInversionVG > VTN3Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate• MOS capacitance is non-linear function of voltage.• Total capacitance in any region dictated by the separation between capacitor plates.• Total capacitance modeled as series combination of fixed oxide capacitanceand voltage-dependent depletion layercapacitance.NMOS Transistor: Structure• 4 device terminals: Gate(G), Drain(D),Source(S) and Body(B).• Source and drain regions form pnjunctions with substrate.•vSB, vDSandvGSalways positive during normal operation.•vSBmust always reverse bias the pnjunctions4The Threshold VoltageVT= VT0+ γ(√|-2φF+ VSB| - √|-2φF|)whereVT0 is the threshold voltage at VSB= 0 and is mostly a function of the manufacturing process– Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.VSBis the source-bulk voltageφF= -φTln(NA/ni) is the Fermi potential (φT= kT/q = 26mV at 300K is the thermal voltage; NAis the acceptor ion concentration; ni≈1.5x1010cm-3at 300K is the intrinsic carrier concentration in pure silicon)γ = √(2qεsiNA)/Coxis the body-effect coefficient (impact of changes in VSB) (εsi=1.053x10-10F/m is the permittivity of silicon; Cox= εox/toxis the gate oxide capacitance with εox=3.5x10-11F/m)The Body Effect0.40.450.50.550.60.650.70.750.80.850.9-2.5 -2 -1.5 -1 -0.5 0VBS(V)VT(V)z VSBis the substrate bias voltage (normally positive for n-channel devices with the body tied to ground)z A negative bias causes VTto increase from 0.45V to 0.85VNMOS Transistor: Triode Region Characteristics5• It is to be noted that the VDSmeasured relative to the source increases from 0 to VDSas we travel along the channel from source to drain. This is because the voltage between the gate and points along the channel decreases from VGSat the source end to VGS-VDS.• When VDSis increased to the value that reduces the voltage between the gate and channel at the drain end to Vtthat is ,•VGS-VDS=Vtor VDS= VGS-Vtor VDS(sat) ≥ VGS-VtConcept of Asymmetric ChannelTransistor in Saturation ModeSDBGVGSVDS > VGS-VTIDVGS-VT-+n+ n+Pinch-offAssuming VGS > VTVDSThe current remains constant (saturates).NMOS Transistor: Saturation RegionTNGSDSTNGSDVvvVvLWnKi −≥−=for 2'2vDSAT=vGS−VTNis called the saturation or pinch-off voltageChannel-Length Modulation•As vDSincreases abovevDSAT,the length of the depleted channel beyond pinch-off point, DL, increases and actual L decreases.•iDincreases slightly with vDSinstead of being constant. iD=Kn'2WLvGS−VTN      21+λvDS      λ = channel length modulation parameter6(µpCox)Channel-Length Modulation•As vDSincreases abovevDSAT,the length of the depleted channel beyond pinch-off point, DL, increases and actual L decreases.•iDincreases slightly with vDSinstead of being constant. iD=Kn'2WLvGS−VTN      21+λvDS      λ = channel length modulation parameter7Enhancement-Mode PMOS Transistors: Structure• p-type source and drain regions in n-type substrate.•vGS< 0 required to create p-type inversion layer in channel region• For current flow, vGS< vTP• To maintain reverse bias on source-substrate and drain-substrate junctions, vSB< 0 and vDB< 0• Positive bulk-source potential causes VTPto become more negative8Depletion-Mode MOSFETS• NMOS transistors with• Ion implantation process is used to form a built-in n-type channel in the device to connect source and drain by a resistive channel• Non-zero drain current for vGS= 0; negative vGSrequired to turn device off.VTN≤09Problem-solving Technique :MOSFET DC Analysis• STep1: Requires knowing the bias condition of the transistor such as cutoff or saturation or nonsaturation.• Step2: If the bias condition is not obvious, one must guess the bias condition before analyzing the circuit.• Step3 How can we Guess?(i) Assume that the transistor is biased in the saturation region, which implies that:VGS>VTN, ID>0, and VDS≥VDS(sat)If all the above conditions are satisfied, analyze the circuit using the saturation current voltage relations.(ii) If VGS<VTN, then transistor is probably in cutoff mode.(iii) If VDS<VDS(sat), the transistor is likely biased in nonsaturation region, analyze the circuit using nonsaturationcurrent voltage relations.MOSFET Circuit Symbols•(g) and (i) are the most commonly used symbols in VLSI logic design.• MOS devices are symmetric.•In NMOS, n+region at higher voltage is the drain.•In PMOS p+region at lower voltage is the drainSummary of the MOSFETCurrent-Voltage relationshipTable