1Limitation of NMOS inverterExample 16.3NMOS Inverter with Depletion Load• This is an alternate form of the NMOS inverter that uses an enhancement-depletion MOSFET load device with gate and source terminal connected.•This inverter has the advantage of VO= VDD, as well as more abrupt VTC transition region even though the W/L ratio for the output MOSFET is small.•The term depletion modemeans that a channel exists even with zero gate voltage.N-Channel Depletion-Mode MOSFET• In n- channel depletion mode MOSFET, an n-channel region or inversion layer exists under the gate oxide layer even at zero gate voltage and hence term depletion mode.• A negative voltage must be applied to the gate to turn the device off.•Thethreshold voltageis alwaysnegativefor this kind of device.NMOS Inverter with Depletion LoadWith the gate and sourceare connected, VGSL=0. Since the threshold voltageof load transistor is negative, we haveVGSL=0>VTNL= -(VTNL)This implies that load MOSFET is always active. For an active device we canwriteVDSL≥VGSL–VTNL= -VTNL=VTNLbecauseVGSL=0.2NMOS Inverter with Depletion Load (cont.)Case I: when VI<VTND(drive is cutoff): No drain current conduct in either transistor. That means the load transistor must be in the linear region of the operation and the output current can be expressed as fellowsiDL(linear)=KL[2(VGSL-VTNL)VDSL-VDSL2]Since VGSL=0, and iDL=00=-KL[2VTNLVDSL+ VDSL2]Which gives VDSL=0 thusVO= VDDThis is the advantage of the depletion load inverter over the enhancement load inverter.NMOS Inverter with Depletion Load(Cont.)Case II: When VI>VTND(driver turns on)and is biased in the saturation region; however, the load is biased in the nonsaturation region.Under the condition we can write iDD=IDDLKD(VGSD-VTND)2=KL[2(VGSL-VTNL)VDSL-VDSL2] Substituting VGSD=VI, VGSL=0, and VDSL=VDD-VOYields•KD(VI-VTND)2=KL[2(-VTNL)(VDD-VO)-VDD–VO)2]Which relates the input and output voltage as long as the driver is biased in saturation region and load is biased in nosaturation region.Two transition points for NMOS depletion load inverterIn the Figure the point B and C are corresponding the two transition points: one for the load and one for the driver.The transition point for the load is given by,VDSL=VDD-VOtAlso VDSL=VGSL-VTNLBy equating the relations we getVDD-VOt=VGSL-VTNLSince VGSL=0V0t=VDD+VTNLAs we know VTNLis negative. This implies that Vot<VDDThe transition point for the driver is given byVDSD=VGSD-VTNDOr in terms of input and output voltage we can write VOt=VIt-VTNDWhen both devices (driver and load) are in saturation regionWhen both devices are biased in saturation region the Q point lies between point B and C on the load curve, andKD(VGSD-VTND)2= KL(VGSL-VTNL)2Or√KD/KL(VI-VTND)=-VTNLImplies that input voltage is constant as the Q-point passes this region.If we further increased the input voltage, the drive is biased in the nosaturationregion while load is in saturation region. The Q-point moves between C and D on the load curve. For the input/output characteristics we equate two drain current equationKD[2(VGSD-VTND)VDSD-VDSD2] = KL(VDSL-VTNL)2Which becomesKD/KL[2(VI-VTND)VO-Vo2]=-(-VTNL)2Implies that input and output voltages are not linear in this region.3VT Characteristics of NMOS Inverter with Depletion LoadThe Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small.4Transient Analysis of NMOS inverters• The source of capacitance CT2and CT3are the transistor input capacitances and parasitic capacitances due to interconnect lines between the inverter stages.• The constant current over a wide range of VDS provided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter configurations.The rate at Transient Analysis of NMOS inverters (cont.)• The fall time relatively short, because the load capacitor discharges through the large drive transistor.• The raise time is longer because the load capacitor is charged by the current through the smaller load transistor.(W/L)L=1(W/L)D=4F-0.5pFdepletion loadenhancement load51160µW825µW200µW616.2: NMOS Logic CircuitNMOS logic circuits are constructed by connecting driver transistor in parallel, series or series-parallel combinationsto produce required output logic functionNMOS NOR gate• NMOS NOR gate can be constructed by connecting an additional driver transistor in parallel with a depletion load inverter.• The output of a NOR gate is only high when both inputs are at logic 0(low)i.e.• If A=B=logic 0,Then both driver transistors MDAand MDBare in cut off mode and V0=VDD (logic 1)For all other possible inputs V0= 0 (logic 0).For example,If A=high (logic1) and B=low (logic0)Then MDBis in cut off mode and remaining circuit behave as depletion load inverter. However, when both driver transistors are in active mode the value of the output voltage logic 0) is changed.NMOS NOR gate: Special case when all inputs are at logic 1When A=B=logic 1Both driver transistors are switched into nonsaturation regionand load transistor is biased in saturation region. We haveiDL=iDA+iDBBy substituting the values of current equation we can write as,KL(VGSL-VTNL)2 = KDA[2(VGSA-VTNA)VDSA-VDSA2] + KDB[2(VGSB-VTNB)VDSB-VDSB2] Suppose two driver transister are identical, which implies that,KDA=KDB=KDVTNA=VTNB=VTNDAs we know VGSL=0Also from figure VGSA=VGSB=VDDVDSA=VDSB=V0By substituting all these parameters we can write above equation as,(-VTNL)2= 2(KD/KL)[2(VDD-VTND)V0-VO2)Conclusion: The above equation suggested that when the both the driver are in conducting mode, the effective aspect ratio of the NOR gate is double. This further suggested that output voltage becomes slightly smaller when both inputs are high. Because higher the aspect ratio lower the output.Concept of effective width to length ratiosFor the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased..Parallel combinationSeries combination7Next Lecture• Next lecture– CMOS inverter – a static view• Reading assignment – Neamen, 16.3, 16.3.1,