Professors Fearing White EE42 100 Problem Set 12 Due at 12 00 pm Thurs Dec 8 in box in 240 Cory Hall Please put Discussion section TA Name on problem set Fall 2005 1 Circuit Review 15 pts a Find Vout b Find the Thevinin equivalent circuit 2 Transient Review 15 pts In the circuit above switch is open for t 0 then closed at t 0 then opened again at t 10ms a Determine vc t for t 0 b Sketch vc t for t 0 3 Op Amp Review 15 pts Determine the Thevinin Equivalent with respect to terminals A and B 4 Diode Review 15 pts a Plot Vout vs Vin Diode is ideal with Von 0 6V b Let Vin t 5 cos 2 t Plot Vout t 5 Logic Design Review 15 pts Consider a logic function F which has three inputs A B C The function F is false when all inputs are false or all inputs are true Otherwise F is true a List the truth table for F b Use a Karnaugh map to find the minimal sum of products form for F c Draw the logic diagram for F minimal sum of products using minimal NAND NOR and NOT gates d Draw a timing diagram assuming unit gate delays ABC follows the sequence 100 111 110 001 000 011 101 changing to each next value after a unit delay e Draw the circuit diagram for part c using PMOS and NMOS transistors in standard CMOS gates 6 Op Amp review 20 pts Let R6 100K C4 100nF R7 10K R8 20K supply voltage for op amp V1 10V a Plot Vo vs vT Note op amp labelled comp is not running in negative feedback b Sketch vT t 7 Load Line Review 15 pts Let Io 1 0mA R 5K a Estimate possible operating points for I V b By hooking up some external components and switch es could you change from one operating point to another By the way this is an obscure kind of flip flop 8 Phasor Review Class D Output 15 pts Let L1 20 H C1 0 5 F R1 4 Vin 50cos t a Write expressions for VL and phase VL b Sketch VL and phase VL c Determine a good value for so that the filter would block just about all of the cosine term e g VL 0 001 V
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