1SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test1SoC Manufacturing Test• SoC Testability Features– Boundary Scan– P1500 standard• SoC Testing Costs• Built-In Self Test• Testing Mixed-Signal Components– “Alternate” test• Defect Tolerance• Error Detection and Fault Tolerance• Loopback test of Mixed-Signal SoCsSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test2The Manufacturing Test Problem1982 1985 1988 1991 1994 1997 2000 2003 2006 2009Cost : Cents / 10,000 Transistors1000.00100.0010.001.000.100.01IC MfgCostCost ofTestMixed SignalDigital2SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test3Partitioning for SoC Test• Partition according to test methodology:– Logic blocks– Memory blocks– Analog blocks• Provide test access:– Boundary scan– Analog test bus• Provide test-wrappers for coresSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test4DFT Architecture for SOCTRSTUser defined test access mechanism (TAM) Module1TestwrapperTestsourceTestsinkModuleNTestwrapperTest access port (TAP) FunctionalinputsFunctionaloutputsFunc.inputsFunc.outputsSOC inputsSOC outputsTDITCKTMSTDOInstruction register controlSerial instruction dataSource: Bushnell and Agrawal3SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test5Scan• Convert each flip-flop to a scan register– Only costs one extra multiplexer• Normal mode: flip-flops behave as usual• Scan mode: flip-flops behaveas shift register• Contents of flopscan be scannedout and new values scanned inFlopQDCLKSISCANscan outscan-ininputsoutputsFlopFlopFlopFlopFlopFlopFlopFlopFlopFlopFlopFlopLogicCloudLogicCloudSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test6Scannable Flip-flops01FlopCLKDSISCANQDXQQ(a)(b)SCANSIDXQQSIss(c)dddsSCAN4SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test7Scan Design and Delay TestCircuitunderTestNeed two patterns for delay testShifting in second pattern changes state of the nodesSolutions: Scan Shifting or Last Shift LaunchFunctional Justification or Broadside TestSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test8Tri-Scan SchemeBased on state holding property of CMOStri5SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test9Tri-Scan Schemescanenablescan_inscan_outtristatebufferSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test10Voltage at Tri-stated output w.r.t. time      6SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test11Boundary Scan• Testing boards is also difficult– Need to verify solder joints are good• Drive a pin to 0, then to 1• Check that all connected pins get the values• Through-hold boards used “bed of nails”• SMT and BGA boards cannot easily contact pins• Build capability of observing and controlling pins into each chip to make board test easierSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test12Boundary Scan (IEEE 1149.1)7SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test13Boundary Scan ExampleSer ial Dat a InSerial Data OutPackage InterconnectIO pad and Boundary ScanCel lCHIP ACHIP B CHIP CCHIP DSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test14Boundary Scan Interface• Boundary scan is accessed through five pins– TCK: test clock– TMS: test mode select– TDI: test data in– TDO: test data out– TRST*: test reset (optional) • Chips with internal scan chains can access the chains through boundary scan for unified test strategy.8SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test15System View of InterconnectSource: Bushnell and AgrawalSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test16Boundary Scan Chain ViewSource: Bushnell and Agrawal9SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test17Elementary Boundary Scan CellSource: Bushnell and AgrawalSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test18SAMPLE / PRELOAD InstructionPurpose:1. Get snapshot of normal chip output signals2. Put data on bound. scan chain before next instr.Source: Bushnell and Agrawal10SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test19EXTEST Instruction Purpose: Test off-chip circuits and board-level interconnectionsSource: Bushnell and AgrawalSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test20INTEST Instruction Purpose:1. Shifts external test patterns onto component2. External tester shifts component responses outSource: Bushnelland Agrawal11SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test21RUNBIST Instruction Purpose: Allows issue of BIST command to component through JTAG hardware Optional instruction Lets test logic control state of output pins1. Can be determined by pin boundary scan cell2. Can be forced into high impedance state BIST result (success or failure) can be left in boundary scan cell or internal cell§ Shift out through boundary scan chain May leave chip pins in an indeterminate state (reset required before normal operation resumes) Source: Bushnell and AgrawalSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test22BYPASS Instruction Purpose: Bypasses scan chain with 1-bit registerSource: Bushnell and Agrawal12SoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test23 Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers.Additional DFT ComponentsSource: H. KerkhoffSoC Design, Fall 2009November 14, 2009J. A. AbrahamSoC Manufacturing Test24 .