1EE382V-ICS:System-on-a-Chip (SoC) DesignAndreas GerstlauerElectrical and Computer EngineeringUniversity of Texas at [email protected] Synthesis and ArchitecturesSource: D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Chapter 6: Hardware Synthesis, Springer, 2009.EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 2Outline• Design flow• RTL architecture• Input specification• Specification profiling• RTL synthesis• Variable merging (Storage sharing)• Operation Merging (FU sharing)• Connection Merging (Bus sharing)• Chaining and multi-cycling• Data and control pipelining• Scheduling• Component interfacing• Conclusions2EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 3Hardware Synthesis Design FlowTool ModelRTLComponentLibrarySpecificationRTL ModelModel GenerationRTL ToolsCompilationEstimationHLSAllocation Binding Scheduling...• Compilation• Estimation• HLS• Model generation• RTL synthesis• Logic synthesis• LayoutEE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 4Hardware Synthesis Design flow• RTL architecture• Input specification• Specification profiling• RTL synthesis• Variable merging (Storage sharing)• Operation Merging (FU sharing)• Connection Merging (Bus sharing)• Chaining and multi-cycling• Data and control pipelining• Scheduling• Component interfacing• Conclusions3EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 5RTL Processor Architecture•Controller• FSM controller• Programmable controller•Datapath components• Storage components• Functional units• Connection components•Pipelining• Functional unit • Datapath• Control•Structure• Chaining•Multicycling•Forwarding• Branch prediction• CachingEE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 6RTL Processor with FSM ControllerOutput LogicB1B2ALUMemoryRF MULB3FSM ControllerInput LogicDatapathControlInputsControlOutputsControlSignalsStatusSignalsDataInputsDataOutputs•Simple architecture•Small number of states4EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 7StatusAddressIR or CWRCmemorPMem AGSRPCB1B2ALUMemoryRF MULB3Programmable ControllerDatapathOffsetControlInputsControlOutputsControlSignalsDataInputsDataInputsRTL with Programmable Control•Complex architecture• Control and datapath pipelining• Advanced structural features •Large number of states (CW or IS)EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 8Outline Design flow RTL architecture• Input specification• Specification profiling• RTL synthesis• Variable merging (Storage sharing)• Operation Merging (FU sharing)• Connection Merging (Bus sharing)• Chaining and multi-cycling• Data and control pipelining• Scheduling• Component interfacing• Conclusions5EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 9Input Specification• Programming language (C/C++, …)• Programming semantics requires pre-synthesis optimization• System description language (SystemC, …)• Simulation semantics requires pre-synthesis optimization• Control/Data flow graph (CDFG)• CDFG generation requires dependence analysis• Finite state machine with data (FSMD)• State interpretation requires some kind of scheduling• RTL netlist• RTL design that requires only input and output logic synthesis• Hardware description language (Verilog / VHDL)• HDL description requires RTL library and logic synthesisEE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 10C Code for Ones CounterFunction-based C code RTL-based C code01: int OnesCounter(int Data){02: int Ocount = 0;03: int Temp, Mask = 1;04: while (Data > 0) {05: Temp = Data & Mask;06 Ocount = Data + Temp;07: Data >>= 1;08: }09: return Ocount;10: }01: while(1) {02: while (Start == 0);03: Done = 0;04: Data = Input;05: Ocount = 0;06: Mask = 1; 07: while (Data>0) {08: Temp = Data & Mask;09: Ocount = Ocount + Temp;10: Data >>= 1;11: }12: Output = Ocount;13: Done = 1;14: }• Programming language semantics• Sequential execution, • Coding style to minimize coding• HW design• Parallel execution, • Communication through signals6EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 11CDFG for Ones Counter01>00DoneOutputInput0Done0Ocount1MaskData&>>1 +DoneDataDoneOcountDataStartData1Mask Ocount• Control/Data flow graph• Resembles programming language• Loops, ifs, basic blocks (BBs)• Explicit dependencies• Control dependences between BBs• Data dependences inside BBs• Missing dependencies between BBsEE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 12FSMD for Ones Counter• FSMD more detailed then CDFG• States may represent clock cycles• Conditionals and statements executed concurrently• All statement in each state executed concurrently• Control signal and variable assignments executed concurrently• FSMD includes scheduling• FSMD doesn't specify binding or connectivity7EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 13CDFG and FSMD for Ones CounterEE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 14RTL Specification for Ones CounterS0S7S4S6S5S4S3S2S1S0StateNext1XXS701XS6XXXXXX10StartInputs: Output:Present0XS500S60XS40XS30XS20XS1XXS0XXS0DoneData = 0StateRF[0] = Data, RF[1] = Mask, RF[2] = Ocount, RF[3] = TempRF[2]RF[0]RF[2]RF[0]RF[2]RF[2]XXRF Read Port AXpassaddANDincrementsubtractXXALUXXRF[3]RF[1]XRF[2]XXRF Read Port BXB3B3B3B3B3InportXRF selectorXshift rightpasspasspasspassXXShifterdisableRF[0]RF[2]RF[3]RF[1]RF[2]RF[0]XRF WriteenableS7ZS6ZS5ZS4ZS3ZS2ZS1ZS0OutportStateOutput logic tablestatusOutput LogicB1ALUShifterB3FSM ControllerInput LogicDatapathDoneStartB2SelectorOutportControlSignalsInportRF Input logic table• RTL Specification• Controller and datapath netlist• Input and output tables for logic synthesis• RTL library needed for netlist8EE382V-ICS: SoC Design © 2009 D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner 15HDL description of Ones Counter01: // …02: always@(posedge clk) 03: begin : output_logic04: case (state)05: // …06: S4: begin 07: B1