Dataflow Modeling of Signal Processing and Communication SystemsOutlineNeeds for System-Level DesignNeeds for Embedded RealizationDataflow ModelsSynchronous Dataflow [Lee 1987]Synchronous Dataflow (SDF)Dataflow Models in Design ToolsSlide 9Homogeneous OperationsSlide 11Increasing Sampling RatePolyphase Filter Bank FormDecreasing Sampling RateSlide 15Slide 16Spectral Shaping for ConverterNoise-Shaped Feedback CodingSlide 19Communication SystemsSlide 21Quadrature Amplitude ModulationQuad. Amplitude DemodulationModeling of Points In-BetweenLimitations of SDFConclusionSlide 27Dataflow Modeling ofSignal Processing and Communication SystemsWireless Networking and Communications GroupJanuary 14, 2019Prof. Brian L. EvansGuest Lecture forEE 382V Embedded System Design and Modeling2OutlineIntroductionSignal processing system design needsSynchronous dataflowSignal processing building blocksFiltersRate changersSignal processing examplesCommunication system examplesConclusion23Needs for System-Level DesignSignal processing algorithmsMultirate processing: e.g. interpolationLocal feedback: e.g. IIR filtersIteration: e.g. decodingGraphical representationsBlock diagram syntax natural but staticDataflow semantics for signal processingSignal representationsBit, byte, integer, fixed-point, floating-pointComplex-valued versions of aboveVectors/matrices of scalar data typesDo not needrecursionOften iterativeBit error rate vs. Signal-to-noise ratio (Eb/No)44Needs for Embedded Realization Block-based and point-by-point processingRetarget simulation for embedded platformsProcessors (e.g. DSPs) and hardware (e.g. FPGAs)Cosimulation on desktop and embedded platformsStatic schedulingPrediction of resources (e.g. memory) at compile timeDSPs have limited on-chip memory (32-512 kB)FPGAs have limited on-board memory & logic blocksFloating-point to fixed-point conversion55Dataflow ModelsMatch data-intensive processingSignal processingCommunication systemsDefinitions [Lee]A token is a data value or data structureA signal is a sequence of tokensA node maps input tokens onto output tokensSet of firing rules specify when a node can fireA firing of a node consumes input tokens and produces output tokensA sequence of firings is a dataflow process66Synchronous Dataflow [Lee 1987]UntimedArcs: one-way first-in first-out (FIFO) queuesNodes: functional blocksSource nodes always enabledOthers enabled when enoughsamples are on all inputsNode executionConsumes same fixed number of samples on each input arcProduces same fixed number of tokens on each output arcConsumed data is dequeued from arcFlow of data through graph does not depend on data valuesA3B277Synchronous Dataflow (SDF)Delay of (n) samplesn samples initially in FIFO queueSystems are determinateExecution in sequence or parallelhas same outcome (predictable)Systems can be statically analyzedCheck for “sampling rate” consistencyDetermine/optimize FIFO queue sizes atcompile timeModels systems with rational rate changesA3B2(6) 23Nodes are not multirate but graph is!Periodic schedule fires A twice & B thrice, e.g. AABBB or ABABB88Dataflow Models in Design ToolsDesign Tool Dataflow Model(s) Example ApplicationsAgilent Advanced Design SystemSynchronous and Timed Synchronous DataflowMixed analog, digital, and RF communication systemsCoware Signal Proc. WorksystemSynchronous and Dynamic DataflowPeriodic digital systems, e.g. transceivers & MP3 decodersNational Instruments LabVIEWHomogeneous Dynamic Dataflow (G)Periodic and aperiodic digital systemsSynopsys CoCentric System Design StudioCyclostatic Dataflow Periodic digital systems, e.g. transceivers & mp3 decodersUC Berkeley Ptolemy ClassicSynchronous and Dynamic DataflowPeriodic and aperiodic digital systems9OutlineIntroductionSignal processing system design needsSynchronous dataflowSignal processing building blocksFiltersRate changersSignal processing examplesCommunication system examplesConclusion910Homogeneous OperationsPointwise arithmetic operations (addition, etc.)Delay by m samples property of SDF arcFinite impulseresponse filter0a1 11 11op0a1 11mz][kx1z][ky0a1Ma2Ma1a……1z1z10][ ][Mmmmkxaky11FIR11Homogeneous OperationsInfiniteimpulseresponsefilterx[k]y[k]y[k-M]x[k -1]x[k-2]b2b1b0UnitDelayUnitDelayUnitDelayx[k-N]bNFeed-forwarda1a2y[k -1]y[k-2]UnitDelayUnitDelayUnitDelayaMFeedbackMmmNnnmkyankxbky10][ ][ ][IIR1212Increasing Sampling RateUpsampling by L denoted as LOutputs input sample followed by L-1 zerosIncreases sampling rate by factor of LFinite impulse response (FIR) filter g[m]Fills in zero values generated by upsamplerMultiplies by zero most of time(L-1 out of every L times)Sometimes combined intorate changing FIR blockmOutput of Upsampler by 41 2 3 4 5 6 7 801 2Output of FIR Filter3 4 5 6 7 8m01 2Input to Upsampler by 4n0g[m ] 41411FIR141313Polyphase Filter Bank FormFilter bank (right) avoids multiplication by zeroSplit filter g[m] into L shorter polyphase filters operating at lower rate (no loss in output precision)Saves factor of L in multiplications and prev. inputs stored and increases parallelism by factor of L g0[n]g1[n]gL-1[n]s(Ln)s(Ln+1)s(Ln+(L-1))g[m] LOversampling filter a.k.a. Pulse shaper a.k.a. Linear interpolatorMultiplies by zero (L-1)/L of the time1LL114Decreasing Sampling RateFinite impulse response (FIR) filter g[m]Typically a lowpass filterEnforces sampling theoremDownsampling by L denoted as LInputs L samplesOutputs first sample and discards L-1 samplesDecreases sampling rate by factor of LSometimes combined intorate changing FIR block 441g[m ]1 11 2Input to Downsampler3 4 5 6 7 8m01 2Output of Downsamplern0FIR411515Polyphase Filter Bank FormFilter bank (right) only computes values outputSplit filter h[m] into M shorter polyphase filters operating at lower rate (no loss in output precision)Saves factor of M in multiplications and increases parallelism by factor of L h0[n]h1[n]hM-1[n]h[m] Ms(Mn)s(Mn+1)s(Mn+(M-1))Undersampling filter a.k.a. Matched filter + sampling a.k.a.Linear decimatorOutputs discarded (M-1)/M of the time11M M16OutlineIntroductionSignal processing system design needsSynchronous dataflowSignal processing building blocksFiltersRate changersSignal