Catapult C®SynthesisHigh Level Synthesis WebinarStuart ClubbTechnical Marketing EngineerApril 2009Catapult Webinar - April 20092Agenda How can we improve productivity? C++ Bit-accurate datatypes and modeling Using C++ for hardware design— A reusable, programmable, variable decimator Synthesizing, optimizing and verifying our C++— Live demoCatapult Webinar - April 20093How can we improve productivity Designs bring ever increasing complexity More complex designs require more— Time— People— Resources Increase of “Gates Per Day” for RTL has stalled— Time to validate algorithm— Time to code RTL— Time to Verify RTLCatapult Webinar - April 20094Productivity Bottlenecks Finding an algorithm’s optimal hardware architecture and implementing it in a timely manner Reducing the number of bugs introduced by the RTL design process Verification of the RTL implementation to show that it matches the original algorithmCatapult Webinar - April 20095 Manual Steps1. Define micro-architecture2. Write RTL3. Optimize area/speed through RTL synthesis Drawbacks1. Disconnect causes design errors2. RTL hard-codes technology making re-use impractical3. Manual RTL coding too time-consuming leading to fewer iterations and sub-optimal designs4. Designs typically overbuiltFloating PointModelFixed PointModelMicro-architectureDefinitionRTLDesignRTL Area/TimingOptimizationRTLSynthesisPlace & RouteHardwareASIC/FPGAManualMethodsLogic Analyzer+C/C++Precision RTLor DCASIC or FPGAVendor AlgorithmDescriptionSystem DesignerHardware DesignerVendorTypical RTL Design FlowThe RTL Flow: Past HistoryCatapult Webinar - April 20096Floating PointModelFixed PointModelMicro-architectureDefinitionRTLDesignRTL Area/TimingOptimizationRTLSynthesisPlace & RouteHardwareASIC/FPGAManualMethodsLogic Analyzer+C/C++Precision RTLor DCASIC or FPGAVendor AlgorithmDescriptionSystem DesignerHardware DesignerVendorTypical RTL Design FlowTraditional Flow vs. Catapult FlowHardwareASIC/FPGAPlace & RouteRTLSynthesisCatapultSynthesisConstraintsLogicAnalyzerFloating PointModelFixed PointModelMicro-architectureDefinitionRTLDesignRTL Area/TimingOptimizationRTLSynthesisPlace & RouteHardwareASIC/FPGAManualMethodsLogic Analyzer+Precision RTLor DCASIC or FPGAVendor AlgorithmDescriptionSystem DesignerHardware DesignerVendorTypical RTL Design FlowCatapult Design FlowFloating PointModelFixed PointModelAlgorithmDescription+ Fewer bugs - Safer design flow Shorter time to RTL More efficient methodology Design optimized through incremental refinementCatapult Webinar - April 20097C++ Bit Accurate Data Types SystemC data types or Mentor Graphics Algorithmic C data types Hardware Designers need exact bit widths— Extra bits costs gates ($$) and performance ($$) Rounding and Saturation are important Simulating what you will synthesize is key— Simulation speed affects validation efforts Catapult Webinar - April 20098SystemC DataTypes Limited Length Integer and Fixed-point— sc_int/sc_uint – maximum 64-bit integer result— sc_fixed_fast/sc_ufixed_fast actually based on a double with maximum 53-bit fixed-point result— Problems mixing signed and unsigned (sc_int<2>) -1 > (sc_uint<2>) 1 returns true! Arbitrary Length Integer and Fixed Point— Resolves most, but not all, issues of ambiguity/compatibility— Slow simulation with fixed-point— Fixed point conditionally compiled due to speed SC_INCLUDE_FXCatapult Webinar - April 20099Mentor Graphics “Algorithmic C” types Fixed-point and Integer types Faster execution on same platform— >200x faster than SystemC types Easy to use, consistent, with no ambiguity Parameterized— Facilitate reusable algorithmic development Built in Rounding and Saturation modes Freely available for anyone to downloadhttp://www.mentor.com/eslCatapult Webinar - April 200910Templatized AC Fixed Data Types W = Overall Width I = Number of integer bits S = signed or unsigned (boolean) Q = Quantization mode O = Overflow modeac_fixed<W,I,S,Q,O> my_variableac_fixed<8,1,true,AC_RND,AC_SAT> my_variable ;“0.0000000” 8-bit signed, round & saturateac_fixed<8,8,true,AC_TRN,AC_WRAP> my_variable ;“00000000” 8-bit signed, no fractional bits.Catapult Webinar - April 200911Using C++ for hardware design Function call with all I/O on the interface— Represents the I/O of the algorithm C++ object-oriented reusable hardware— Technology, implementation, and Fmax independent— Multiple instantiations of functions (objects) with state RTL component instantiation— Instantiations with differing implementations RTL VHDL architecturesCatapult Webinar - April 200912A programmable variable decimator Programmable ratio (phases) Tap Length based on decimation factor and ‘N’— x1 decimation = 1 * N taps; — x4 decimation = 4 * N taps— x8 decimation = 8 * N taps Seamless transitions between output rates— Two sets of externally programmable coefficients— Centered delay line accessCatapult Webinar - April 200913Top Level Filter function Simple instantiation of templatized class Call member function “decimator_shift” Write the member function once— Implement a filter with any tap length, and any data typesvoid my_filter (ac_channel<d_type> &data_in,ratio_type ratio,bool sel_a,c_type coeffs_a[N_TAPS_1*N_PHASES_1],c_type coeffs_b[N_TAPS_1*N_PHASES_1],ac_channel<d_type> &data_out) {static decimator<ratio_type,d_type,c_type,a_type,N_TAPS_1,N_PHASES_1> filter_1 ;filter_1.decimator_shift(data_in,ratio,sel_a,coeffs_a,coeffs_b,data_out) ;}typedef’s for data types passed to class objectCatapult Webinar - April 200914Data types used in this example Use of AC data types for bit-accurate modeling and Synthesis ensures 100% match between RTL and C++#define N_TAPS_1 8#define N_PHASES_1 8#define LOG_PHASES_1 3#define DATA_WIDTH 8#define COEFF_WIDTH 10typedef ac_fixed<DATA_WIDTH,DATA_WIDTH,true,AC_RND,AC_SAT> d_type ;typedef ac_fixed<COEFF_WIDTH,1,true,AC_RND,AC_SAT> c_type ;typedef ac_fixed<DATA_WIDTH+COEFF_WIDTH+7,DATA_WIDTH+7+1,true> a_type ;// 0 to 7 ratetypedef ac_int<LOG_PHASES_1,false> ratio_type ;Data type will round and saturate when writtenFull Precision Accumulator- Saturation is order dependent3-bit unsigned for decimation ratioCatapult Webinar - April 200915template <class rType, class dType, class cType, class aType, int N_TAPS, int N_PHASES>class decimator {// data membersdType