1EE382 – System-on-Chip Design - ESL Languages SPS-1 University of Texas at AustinTransaction-Level Modeling andElectronic System-Level LanguagesSteven P. SmithSoC DesignEE382VFall 2009EE382 – System-on-Chip Design - ESL Languages SPS-2 University of Texas at AustinOverview• Motivation: Why have ESL languages?• Transaction-Level Modeling• Levels of abstraction in modeling• Basic requirements of ESL languages• ESL languages and environments: trade-offs• An overview of a sampling of ESL languages• What’s missing from current ESL languages?• Conclusions2EE382 – System-on-Chip Design - ESL Languages SPS-3 University of Texas at AustinMotivation• Why use transaction-level modeling and ESL languages?• Manage growing system complexity• Move to higher levels of abstraction• Enable HW/SW co-design• Speed-up simulation• Support system-level design and verification Increase designer productivity Reduce development costs and risk Accelerate time-to-market & time-to-moneyEE382 – System-on-Chip Design - ESL Languages SPS-4 University of Texas at AustinTransaction-Level Modeling• Communication among modules occurs at thefunctional level.• Each transaction is a coherent unit of interaction • Data structures and object references are passed instead of bit vectors• Goals of TLM• Higher level of abstraction• More comprehensible high-level system models• Greater simulation speeds• Advantages of TLM• Natural way to think about high-level communications • Object Independence• Abstraction Independence3EE382 – System-on-Chip Design - ESL Languages SPS-5 University of Texas at AustinTransaction-Level ModelingMemoryManagementUnitSystemMemoryrequest burst read, size = cache line bytesreturn cache lineMemoryManagementUnitSystemMemory &Bus Controllerdrive address, read request control signalsdrive acknowledge of burst read requestdrive first data word onto busassert bus master requestgrant busdrive last data word onto bus…release busTransaction-LevelExampleSequenceRTLExampleSequenceEE382 – System-on-Chip Design - ESL Languages SPS-6 University of Texas at AustinElements of Transaction-Level Modeling• Transaction-Level Modeling = < {objects}, {compositions} >• Object = {computation object} | {communications object}• Composition• Computation objects send and receive abstract data via communications objects.• Advantages of TLM• Object Independence• Abstraction Independence* Definition from Gajski and Cai, UC Irvine4EE382 – System-on-Chip Design - ESL Languages SPS-7 University of Texas at AustinA. "Specification model" "Untimed functioal models"B. "Component-assembly model" "Architecture model" "Timed functonal model"C. "Bus-arbitration model" "Transaction model"D. "Bus-functional model" "Communicatin model" "Behavior level model"E. "Cycle-accurate computationmodel"F. "Implementation model" "Register transfer model"ComputationCommunicationA BCD FUn-timedApproximate-timedCycle-timedUn-timedApproximate-timedECycle-timedLevels of Abstraction• Consider models as a function of their time-granularity* Figure and taxonomy by Gajski and Cai, UC IrvineA. Specification Model“‘Untimed’ Functional Models”B. Component-Assembly Model“Architecture Model”“’Timed’ Functional Model”C. Bus-Arbitration Model“Transaction Model”D. Bus-Functional Model“Communication Model”“Behavior-Level Model”E. Cycle-Accurate Computation ModelF. Implementation Model“Register-Transfer Level (RTL) Model”EE382 – System-on-Chip Design - ESL Languages SPS-8 University of Texas at AustinSpecification Model* Figure and taxonomy by Gajski and Cai, UC IrvineObjects:Computation:BehaviorsCommunication:VariablesComposition:HierarchyExecution OrderSequentialParallelPipelinedStatesSynchronization:Notify/Waitv2 = v1 + b*b;v3= v1- b*b;v1v1 = a*a;v2v4 = v2 + v3;c = sequ(v4);B1B2v3B3B4B2B3ComputationCommunicationA BCD FUn-timedApproximate-timedCycle-timedUn-timedApproximate-timedECycle-timed5EE382 – System-on-Chip Design - ESL Languages SPS-9 University of Texas at AustinComponent-Assembly Model* Figure and taxonomy by Gajski and Cai, UC IrvineObjects:Computation:ProcessorsMemoriesIPCommunications:Variable ChannelsComposition:HierarchyExecution OrderSequentialParallelPipelinedStatesSynchronization:Notify/Waitv3v3= v1- b*b;B3v4 = v2 + v3;c = sequ(v4);B4PE3v2 = v1 + b*b;B2PE2v1 = a*a;B1PE1cv2cv12cv11ComputationCommunicationA BCD FUn-timedApproximate-timedCycle-timedUn-timedApproximate-timedECycle-timedEE382 – System-on-Chip Design - ESL Languages SPS-10 University of Texas at AustinBus-Arbitration Model* Figure and taxonomy by Gajski and Cai, UC IrvineObjects:Computation:ProcessorsMemoriesIP, arbitersCommunications:Abstract Bus ChannelsComposition:HierarchyExecution OrderSequentialParallelPipelinedStatesSynchronization:Notify/Waitv2 = v1 + b*b;B2PE2v1 = a*a;B1PE1v3v3= v1- b*b;B3v4 = v2 + v3;c = sequ(v4);B4PE3cv12cv11cv2PE4(Arbiter)31 21. Master interface2. Slave interface3. Arbiter interfaceComputationCommunicationA BCD FUn-timedApproximate-timedCycle-timedUn-timedApproximate-timedECycle-timed6EE382 – System-on-Chip Design - ESL Languages SPS-11 University of Texas at AustinBus-Functional Model* Figure and taxonomy by Gajski and Cai, UC IrvineObjects:Computation:ProcessorsMemoriesIP, arbitersCommunications:Protocol Bus ChannelsComposition:HierarchyExecution OrderSequentialParallelPipelinedStatesSynchronization:Notify/Waitv2 = v1 + b*b;B2PE2v1 = a*a;B1PE1v3v3= v1- b*b;B3v4 = v2 + v3;c = sequ(v4);B4PE3PE4(Arbiter)31 21: mast er i nt er f ace2: sl ave i nt er f ace3: arbitor interfacereadyackaddress[15:0]data[31:0]IProtoco lSlavereadyackaddress [15:0]data[31:0]ComputationCommunicationA BCD FUn-timedApproximate-timedCycle-timedUn-timedApproximate-timedECycle-timedEE382 – System-on-Chip Design - ESL Languages SPS-12 University of Texas at AustinCycle-Accurate Computation Model* Figure and taxonomy by Gajski and Cai, UC IrvineObjects:Computation:ProcessorsMemoriesIP, arbitersWrappersCommunications:Abstract Bus ChannelsComposition:HierarchyExecution OrderSequentialParallelPipelinedStatesSynchronization:Notify/WaitPE3cv12cv11cv231 21. Master interface2. Slave interface3. Arbiter interface4. WrapperS0S1S2S3S4PE4S0S1S2S344PE2PE1MOV r1, 10MUL r1, r1, r1.......MLA r1, r2, r2, r1....44ComputationCommunicationA BCD FUn-timedApproximate-timedCycle-timedUn-timedApproximate-timedECycle-timed7EE382 –