DOC PREVIEW
UT EE 382V - General Purpose Processors- Binary Compatibility

This preview shows page 1-2 out of 7 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 7 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 7 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 7 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

EE382V: Computer Architecture: User System Interplay Lecture #03Department of Electical and Computer EngineeringThe University of Texas at Austin Monday, 29 January 2007Disclaimer: ”The contents of this document are scribe notes f or The University ofTexas at Austin EE382V Spring 2007, Co mputer Architecture: User System Interplay∗.The notes capture the class discussion and may contain erroneous and unverified infor-mation and comments.General Purpose Processors: Binary CompatibilityLecture #03: Monday, 29 January 2007Lecturer: Mattan ErezScribe: Paul ZucknickReviewer: Min Kyu Jeong1 The Transmetta Code Morphing Software: UsingSpeculation, Recovery, and Adaptive Retransla-tion to Address Real-Life Challenges1.1 ReferenceReferences[1] Dehnert, J.C.; G r ant, B.K.; Banning, J.P.; Johnson, R.; Kistler, T.; Kla iber, A.;Mattson, J., “The Transmeta Code MorphingTMSoftware: using speculation, recov-ery, and a da ptive retranslation to address real-life challenges,” I nternational Sym-posium on Code Generation and Optimization, 2003. CGO 2003., pp. 15- 24, 2 3-26March 2003.1.2 IntroductionThis paper comes from industry. Transmetta’s Crusoe microprocessor is a VLIW micro-processor that along with a software layer, the Code Morphing Software (CMS), providesa full implementation of the x86 architecture. The paper discusses the software systemand the hardwa r e support for implementing x86, specifically exceptions and interrupts,I/O, and self-modifying code.∗Copyright 2007 Paul Zucknick and Mattan Erez, all rights reserved. This work may be reproducedand redistributed, in whole or in part, without prior written permission, provided all copies cite theoriginal source of the document including the names of the copyright holders and ”The University ofTexas at Austin EE382V Spring 2007, Computer Architecture: User System Interplay”.2 EE382V: Lecture #03The CMS software builds on top of a binary translation system. A binary transla-tion system takes an instruction stream from one machine and executes it into one ofmore instructions on another machine. Conversion can be either complex-to-simple orsimple-to-complex. We use binary translation every day (i.e. Java Virtual Machines).Binary translation involves dynamically taking 1 instruction set and translating it toanother instruction set just like a compiler, but not using a high level language. BinaryTranslation is covered in Section III of this paper.Transmetta starts with a simple sleek host ISA and they take the ta rget x86 code andtranslate it to their VLIW architecture. The paper makes the assumption that there is asequential instruction set with Von Neumann Semantics. Von Neumann was the fatherof modern computing (NOTE: t he paper for next t ime tries t o get around the problemsof the Von Neumann model). In the Von Neumann model, a program is composed of aset of instructions and state. Instructions manipulate state with precise semantics. Eachinstruction is executed one at a time and effects everything that follows and everythingelse in the system.To Generalize the paper, the goal was to make the common case fast and efficient inHW and handle the exceptional cases (exceptions, etc) in SW with the CMS system. Thisapproach allows the overall design to be sleeker and perhaps better, but the system runsslower than native x86. The overall idea of the solution is that you gain t he flexibility tochange the underlying ISA and make improvements by using this technique. (This wasnot explicitly stated in the paper).Why would we care about this paper? A flaw of the paper is that the motivationis not mentioned. However, the paper is governed by the implicit assumptions withinthe academic community that improved performance is better. In general as you writea paper you have very little space, and sometimes things end up missing from the finaldraft. We will discuss the missing elements in class.2 Discuss i on Points2.1 What Problem is being Solved?• The number o ne goal of the paper is that the authors are trying to run x86 codeon a VLIW machine. (The key is to run the code correctly, but this is assumed tobe true.)• The authors try to address specific issues with regards to translation (precise ex-ceptions, interrupts, memory-mapped I/O, and self-modifying code)• The authors wa nt the freedom to have the ability to modify the underlying imple-mentation (ISA)• The authors a r e trying to build a system that implements an ISA with both thehardwar e and software and no t just hardware alone.EE382V: Lecture #03 32.2 What is Unique?• The solution uses bo t h HW and SW to implement the ISA.• The solution provides optimizations fo r high performance• The system “Performs” as well as native x86 HW.However, “Perform” is loo sely defined? (assumed to be wall clock time)• The paper claims that their processor uses less power than x86 hardwareThis is an attra ctive point in terms of power but no proof is provided.• The authors want to create a “Robust” design (However, t he definition of robustcould be interpreted in different ways)In general a robust design is a design that meets design goals or a specified targetwithout having a larg e spread in the results.• The solution provides har dware acceleration f or commit and r ollback ( simple /elegant catch all) This enables “efficient” (NOTE: efficient is not defined in thepaper) speculation - no need for compiled bookkeeping code.• There is no reliance on the OS• New translation techniques are introduced.The big idea of the paper is the ability to take a piece of code and get the expectedperformance rega r dless of the application without using just HW. The paper presentsa HW/SW combination that goes from a legacy binary and allows it to be run on newsystems with improved performance capabilities. They change the HW implementationwith some benefit to the users and take some more complex things and offload them toSW.2.3 Who are the Intended u sers?• x86 users2.4 What are the goals of the design?• Improved wall clock time.• Reduce power by using less HW (VLIW architecture)• Reduced “cost”– Less cooling– Easier to design4 EE382V: Lecture #03– Easier to verify (is this really true???)– The design actually becomes harder to verify because both the software andhardwar e must be verified.• The goal of the paper wasn’t enable a transition to a VLIW architecture; the goalwa s to utilize the simpler design and use a HW/SW combination.• The


View Full Document

UT EE 382V - General Purpose Processors- Binary Compatibility

Documents in this Course
Load more
Download General Purpose Processors- Binary Compatibility
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view General Purpose Processors- Binary Compatibility and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view General Purpose Processors- Binary Compatibility 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?