ECE 126 – Inverter Tutorial: Mixed Signal Simulation: Using Verilog as Input Stimulus Created at GWU by Thomas Farmer Objectives: • Create a verilog test bench for an inverter • Use the Cadence configuration hierarchy editor tool Assumptions: • Student has a basic familiarity with verilog • Student is familiar with simulating off the ‘extracted view’ of a layout Introduction: Up to this point you have used “pulses” and “dc sources” in your test benches to test your Cadence schematics and layouts. In this lab you will learn to create and use a verilog ‘source’ to test your Cadence schematics and layouts. This will enable you to create more complex test-benches for your final project. LAB SETUP: 1. BEFORE starting cadence, type the following command in a terminal window: cp ~vlsi/ece126/class_material/lab9/.cdsenv ~ (ensure that there are no errors before continuing with this lab) 2. Start Cadence • In the Library Manager, look for a library called: analogLib • If it IS present, skip to section labeled: “Creating a Verilog Driver for an Inverter” • If it is NOT present, proceed to step 3 below 3. Adding library: analogLib • From the CIW window’s menu choose: Tools->Library Path Editor… • When the Library Path Editor window opens, type the following line at the bottom of the list: Library: analogLib Path: /apps/cadence/ic/tools/dfII/etc/cdslib/artist/analogLib • From the menu choose: File->Exit. When prompted to save changes, answer yes. • You will now see the analogLib library in the Library Manager window. CREATING A VERILOG DRIVER FOR AN INVERTER:In lab 2, a pulsed waveform was used to provide stimulus for your inverter. In this section, you will create a verilog-driver (very simple verilog code), to replace the pulsed waveform from lab 2. 1. Create a new cell in your Digital Library, called: inv_tb_vdriver 2. Edit the verilog code: • The “GEDIT” editor should appear • Replace the skeleton verilog code with the following verilog code (copy & paste this code): //Verilog HDL for "Digital", "inv_verilog_driver" "functional" `timescale 10us/1us module inv_tb_vdriver ( test_data ); output test_data; reg test_data; initial begin test_data = 1'b0; #15 $finish; end always #1 test_data = ~test_data; endmodule • What does this code do? - It will create a simple pulse that goes between 1 and 0 for 150us: • `timescale 10us/1us o means that during simulation, each tick of the simulator’s clock will be worth 10us. The 1us on the right of the slash, forces the simulator to keep 1us amount of precision. So we can zoom in to at least 1us of time. • #15 $finish; o Tells the simulator to stop the simulation after 15 ticks of the simulator’s clock. Since each tick is worth 10us, our simulation will end after: 15 x 10us = 150us. • always #1 test_data = ~test_data; o At every single clock tick, the value of the output: test_data, will be inverted. Initially we set test_data to 0. After 1 clock pulse, it will change to 1. After the next clock pulse, it will change to 0, and so on and so on. You must type: functional You must switch the type to: Verilog3. Exit the GEDIT editor, answer SAVE when prompted. • Cadence then compiles the verilog code. Check the CIW and see if there are any errors or warnings. If there are, ensure you copied the code correctly into GEDIT. 4. When prompted to create a symbol for your verilog code, choose “YES” • Cadence automatically generates a symbol for your verilog code. It will have 1 output line called: test_data as you specified in the code. 5. Ensure from the CIW, that there are 0 errors and 0 warnings in your verilog driver code: • Now that you have created the verilog-driver, we will instance it in a test bench for our inverter in the next section.CREATING THE MIXED SIGNAL TEST BENCH USING HEIRARCHY EDITOR: 1. Create a new “schematic” cell in the Digital Library, called: inv_tb2 2. Arrange your schematic as in this picture: • Instance the “inv_tb_vdriver” that you made in the previous section of this tutorial • Instance the “inv” that you made in lab 1 (Digital->inv) • Add wire names: VIN and VOUT to the schematic • Close and Save the inv_tb2 schematic3. Create a new view in the inv_tb2, called: config 4. The Hierarchy Editor will start: Keep inv_tb2 You must change this to “config” Make sure the “Hierarchy Editor” appears here Click on “Use Template”• From the template list, select “spectreVerilog”, press OK • From the template list, select “spectreVerilog”, press OK • After making the above changes, press OK Ensure the cell is: inv_tb2 Change the View to be: schematic Change the Library List to: Digital analogLib NCSU_Analog_Parts Everything else is left at its default value5. The Hierarchy Editor will appear • This editor lists the “views” that the “inv_tb2” will use for each part you’ve instanced in the inv_tb2 schematic. • Look at first line. Notice that the “Digital->inv->schematic” (as opposed to its extracted view) will be used in the simulation. • You could change the “view” to extracted, we will do this later in the tutorial • From the menu choose: view->Update • Press OK to update the inv_tb2 config view (if this window even appears) • From the menu, choose: File->Save • Then exit the Hierarchy EditorRUNNING THE SIMULATION: 1. Once the Hierarchy Editor is closed, from the Library Manager, open the inv_tb2->config view • Click “yes” to open both the config view & schematic view of the inv_tb2 cell. 2. Once the inv_tb2 schematic opens, launch the ADE-L spectre simulator:3. From the menu, choose setup->Simulator/Directory/Host, set the Simulator to “spectreVerilog” • From the simulator menu choose: Setup->Model Libraries • Ensure that the model for your NMOS and PMOS transistor are on the list: • If these two libraries are not on the list, click on the bottom line and add them • Press OK when done4. Setup a 150us Transient Analysis, choose VIN and VOUT as outputs to be plotted as follows: 5. Run the simulation and verify the following output is obtained: • The input changed every 10us (or 1 clock pulse), as you specified in your verilog code • The simulation ended after 150us (or