ECE 126 – NAND Gate Tutorial: Mixed Signal Simulation: Using Verilog as Input Stimulus Created at GWU by Thomas Farmer Objectives: • Create a verilog test bench for a 2-input NAND gate • Use verilog to verify output from a 2-input NAND gate • Use the Cadence configuration hierarchy editor tool Assumptions: • Student has completed the Inverter Tutorial on Mixed Signal Simulation w/ Verilog • Student has a basic familiarity with verilog • Student is familiar with simulating off the ‘extracted view’ of a layout Introduction: Up to this point you have used “pulses” and “dc sources” in your test benches to test your Cadence schematics and layouts. In this lab you will learn to create and use a verilog ‘source’ to test your Cadence schematics and layouts. This will enable you to create more complex test-benches for your final project. LAB SETUP: 1. Ensure you have setup your environment as specified in the Inverter Tutorial on Mixed Signal Simulation w/Verilog 2. Start Cadence • In the Library Manager, look for a library called: analogLib • If it IS present, skip to section labeled: “Using Verilog to Test a 2-Input NAND Gate Layout” • If it is NOT present, proceed to step 3 below 3. Adding library: analogLib • From the CIW window’s menu choose: Tools->Library Path Editor… • When the Library Path Editor window opens, type the following line at the bottom of the list: Library: analogLib Path: /apps/cadence/ic/tools/dfII/etc/cdslib/artist/analogLib • From the menu choose: File->Exit. When prompted to save changes, answer yes. • You will now see the analogLib library in the Library Manager window.NOTE: Many screenshots are omitted from this tutorial, as it is assumed the student is now familiar with the screens from the tutorial: ”Inverter Tutorial on Mixed Signal Simulation w/Verilog” USING VERILOG TO TEST A 2-INPUT NAND GATE LAYOUT: We will now repeat the process, but now for a two-input NAND gate. There are some differences between the work we’ve done in the last section and what must be done for a two-input NAND: • The verilog code is slightly more complicated • The wiring of the test-bench schematic is harder • We will simulate off the extracted view of the NAND’s layout, as opposed to the schematic view. • We will set the threshold voltage for a 1 and 0 (5V and 0V) in the simulator • We will add additional verilog code to verify the NAND’s output, instead of simply generating the input CREATING THE ANALOG-EXTRACTED VIEW: 1. Open the extracted view of the 2-input NAND created in HW #1 • Ensure the view was created with parasitic capacitances (if not, re-extract it) • Bring up the LVS form (Verify->LVS) • Run the LVS and ensure it passes (view the output log to make certain) • After successful LVS, click on “Build Analog” button • Click “OK” on the next form • Ensure there are no errors in the CIW window, then close the LVS and extracted view 2. Return the Library Manager • Ensure there is a NAND-2 “analog_extracted” view for the nand2 cell in the Library Manager • You may open the view if wish; it is identical in appearance to the extracted view • While this view appears identical to the extracted view, it is different at the netlist level. We will make use of this view later in the tutorial.CREATING A VERILOG DRIVER FOR A TWO INPUT NAND GATE: We will now create verilog code to test the two-inputs of the NAND gate 1. Create a new cell in your Digital Library, called: nand2_tb_vdriver 2. Edit the verilog code: • Replace the skeleton verilog code with the following verilog code (copy & paste this code): //Verilog HDL for "Digital", "nand2_tb_vdriver" "functional" `timescale 10us/1us module nand2_tb_vdriver ( test_data, results ); input results ; output [1:0] test_data ; reg [1:0] test_data ; initial begin test_data=2'b00; #1 test_data=2'b01; #1 test_data=2'b10; #1 test_data=2'b11; #1 $finish ; end endmodule • What does this code do? - It will create the four possible input combinations to test the NAND gate: • output [1:0] test_data ; o Notice that this time, the variable: “test_data” is 2-bits wide. • test_data=2'b00; #1 test_data=2'b01; o At the first clock tick, the simulator will set test_data = 00 o A # statement in verilog, indicates a delay. o Because we put the #1 in front of the line, test_data will be set to 01, 1 clock tick after the last line of code was executed. o Because the timescale is set to 10us, #1 will translate to 1 x 10us = 10us. So test_data will be set to 01 after 10us. • #1 $finish ; o Why only #1? Because the #1 is relative to the last line. So this simulation will end after 40us. • input results ; o Why didn’t we use this? We will later in this tutorial, for now it’s a place holder for our symbol. 3. Exit the GEDIT editor, answer SAVE when prompted. 4. When prompted to create a symbol for your verilog code, choose “YES” You must type: functional You must switch the type to: Verilog5. Ensure from the CIW, that there are 0 errors and 0 warnings in your verilog driver code. CREATING THE MIXED SIGNAL TEST BENCH USING HEIRARCHY EDITOR: 1. Create a new “schematic” cell in the Digital Library, called: nand2_tb2 2. Arrange your schematic as follows, wire only as shown in this diagram: • Instance the “nand2_tb_vdriver” that you made in the previous section of this tutorial • Instance the “nand2” that you made in HW 1 (Digital->nand2) • Wire up the output to a capacitor, and label the output ‘results’ • Leave space between the vdriver and the nand2 gate 3. Create a bus wire: • Because the nand2_tb_vdriver has a 2-bit output, we need to create bus wire. • From the schematic menu, choose: Create->Wire (wide) • Create a short wire from the output of the vdriver, do NOT connect it directly to the NAND gate, • End the wire by double clicking• Now use a NARROW wire to connect from the bus to the “A” input of the NAND gate: • Use a second NARROW wire to connect from the bus to “B” input, but make sure to create a separate ‘solder dot’ as show here. Do not connect it to other narrow wire by mistake: • You MUST now wire the bus and the individual wires for the simulator to separate the bus correctly. This step is not optional. •