Homework #0: Inverter SampleThomas FarmerECE 126Professor M.E.ZaghloulOctober 16, 2007ECE 126 Homework #0 Page 1 of 7Author: Thomas Farmer1. Draw the schematic and layout of a CMOS inverter using the CADENCE tool. Size the transistors to make tpHL=tpLH. Calculate the area of the layoutSchematic:Fig 1.1 – Inverter Schematic, PMOS 2.4u/.6u, NMOS 1.5/.6uTest Bench:Fig 1.2 – Inverter Test Bench, CL=10pF, VPULSE 0 to 5V, width=25us, period=50usECE 126 Homework #0 Page 2 of 7Author: Thomas FarmerLayout and Extracted Views: Fig 1.3a – Inverter Layout Fig 1.3b – Extraction of LayoutLVS Report:@(#)$CDS: LVS.exe version 5.1.0 09/12/2006 23:55 (cicsun11) $Command line: /apps/cadence2005/ic5141usr4/tools/dfII/bin/32bit/LVS.exe -dir /home/grad/tfarmer/ece126/LVS -l -s -t /home/grad/tfarmer/ece126/LVS/layout /home/grad/tfarmer/ece126/LVS/schematicLike matching is enabled.Net swapping is enabled.Using terminal names as correspondence points.Compiling Diva LVS rules... Net-list summary for /home/grad/tfarmer/ece126/LVS/layout/netlist count4 nets4 terminals1 pmos1 nmos Net-list summary for /home/grad/tfarmer/ece126/LVS/schematic/netlist count4 nets4 terminals1 pmos1 nmos Terminal correspondence points N3 N4 VIN N2 N3 VOUT N1 N1 gnd! N0 N0 vdd!Devices in the rules but not in the netlist: cap nfet pfet nmos4 pmos4ECE 126 Homework #0 Page 3 of 7Author: Thomas FarmerThe net-lists match. layout schematicinstancesun-matched 0 0rewired 0 0size errors 0 0pruned 0 0active 2 2total 2 2 netsun-matched 0 0merged 0 0pruned 0 0active 4 4total 4 4terminalsun-matched 0 0matched butdifferent type 0 0total 4 4Probe files from /home/grad/tfarmer/ece126/LVS/schematicdevbad.out:netbad.out:mergenet.out:termbad.out:prunenet.out:prunedev.out:audit.out:Probe files from /home/grad/tfarmer/ece126/LVS/layoutdevbad.out:netbad.out:mergenet.out:termbad.out:prunenet.out:prunedev.out:audit.out:Table 1.1 – LVS Report indicating match between Schematic and LayoutECE 126 Homework #0 Page 4 of 7Author: Thomas FarmerSimulations:Fig 1.4a – Transient Simulation of Inverter (Fig 1.2) to show functionality, Total sim. time = 150usFig 1.4b – Transient Simulation of Inverter (Fig 1.2) to show rise time, Total sim. time = 150us, Rise Time = 112nsFig 1.4c - Note: show VTC Graph in this section as wellECE 126 Homework #0 Page 5 of 7Author: Thomas FarmerCalculations/Explanations:To make tpLH=tpHL the PMOS of the inverter was sized to: W/L=2.4um/.6um. The NMOS of the inverter was sized to: W/L=1.2um/.6um. The determination of this size was shown in Fig 1.4c.The total area utilized in the layout of the inverter is: 7.2um x 20.7um = 149.04um2. The determination of this area was shown in Fig 1.3a.ECE 126 Homework #0 Page 6 of 7Author: Thomas Farmer2. Start Each Question on New Page.- Use Header/Footer to ensure your name is on every page- Attempt to print your report in color, double sided. - If color is not available, black and white is acceptable as long as contrast on pictures is adjusted to show salient details.- Include Schematic, Test Benches, Functionality simulations, layout (if asked), LVS (if layout is performed), for all questions. - Never resize a picture so small that details of importance (numbers, measurements, etc.) cannot be read.- If a crucial # is unreadable, no matter what size the picture is, be sure to use the caption under the picture to emphasize it.- If LVS is suspected to have been falsified, you may be required to show results to GTA onyour workstation.ECE 126 Homework #0 Page 7 of 7Author: Thomas