ECE 126 – Logic Gate Creation: 2 input NAND Gate Schematic + Test Bench Created at GWU by Anis Nurashikin Nordin & Thomas Farmer Objectives: • Create a schematic for a 2 input NAND gate • Create a symbol for a 2 input NAND gate • Create a test bench for a 2 input NAND gate, that allows for transient simulation to verify functionality of NAND gate • Create a test bench for a 2 input NAND gate, that allows for a swept DC analysis • Create a layout for a 2 input NAND gate • Create an AND gate using Inverter (from Lab 3) with NAND gate (from this lab) Assumptions: • Student has successfully completed Lab 1, 2, and 3 Part 1: Creating NAND Schematic 1. Login to workstation and start cadence 2. From the Library Manager, click on your “DIGITAL” library o Choose File->New->Cell View… o Fill in the form: o Library Name: Digital o Cell: nand2 o View: schematic o Type: schematic o Application: Schematics-L 3. Instance parts: pmos4, nmos4, vdd, gnd, to create the following schematic o For now, use “minimum” sizes for W/L of each transistor, later you will adjust themo You must “rotate” the PMOS and NMOS SIDEWAYS by doing the following: Before Rotate After Rotate (notice, current flow direction is still the same) o Menu: Edit->rotate or press the letter “r” o Click “Sideways” o Note the current flow direction after you rotate is still correct! (this is important) o You can also rotate the input/output pins as well 4. Check and save schematic, make sure there are no warnings/errorsPart 2: Creating NAND Symbol 1. In the schematic editor, from the menu choose: Create->Cellview->From Cell View o Accept the defaults and press OK o The symbol editor appears 2. Press the “delete” key and click on the green box and red box in the editor o Do NOT delete the PINS or labels for the PINS, if you do, close the window and DO not save, simply restart from step 1 above 3. Create the following symbol: o From the menu choose: Create->Shape->Line, draw the left, top and bottom lines o o Choose “Arc” shape to draw the Arc of the NAND gate o Choose the “Circle” shape to draw the circle of the NAND gate 4. Save and close the symbol 5. Save and close the schematicPart 3: Creating the Functional Test Bench 1. From the Library Manager, click on your “DIGITAL” library o Choose File->New->Cell View… o Fill in the form: o Library Name: Digital o Cell: nand2_tb o View: schematic o Type: schematic o Application: Schematics-L 2. Instance parts: 1 vdd, 4 gnd’s, 2 vpulse, 1 10pF capacitor, and your NAND gate, to create the following schematic: 3. Add “wire names” to the input and output wires: 1. From the menu, choose: Create->Wire Name… 2. Type the letter “A” then click on the wire you wish to name 3. Repeat this process for wires: B and OUT 4. This gives “names” to your nets, as opposed to the random “net7” type names 5. This is very helpful when you are viewing your simulated results4. Select each “Pulse Input,” press the letter “q” and set the “vpulse” properties as follows: vpulse attached to A vpulse attached to B 5. Notice the overlapping periods in the figures above 6. Set the VDC (for VDD) voltage to 5V 7. Set the capacitor to 10pF 8. Save the schematic, and perform a “transient” analysis as follows: • From the menu, choose: Launch->ADE-L • Ensure that you use the “Spectre” simulator • Choose Analysis type to be: “transient” lasting for 150u seconds (notice: that’s about 4 cycles of vpulse B) • Plot the signals of Net’s A, B, and OUT (from the schematic) as shown below (now you see why we labeled the wires) • Run the simulationWhen the resultant graph appears, choose from the menu: Axis->Strips to separate the signals • Is it working? • Look at the graph for A, and B, when they are at 5V, this indicates a logical 1. When it is at 0 volts, this indicates a logical 0. • Write out the truth table for a 2 input NAND gate. • See if the logic values for the “OUT” net match up with your expectations. 9. Once everything is working, save the STATE of the simulator and call it: nand2_functional_test 10. Close the simulator and schematicPart 4: Creating the VTC Test Bench 1. From the Library Manager, click on your “DIGITAL” library • Choose File->New->Cell View… • Fill in the form: o Library Name: Digital o Cell: nand2_tb o View: schematic_vtc o Type: schematic o Application: Schematics-L • By using this View Name, you may see the following error message: o Answer YES to this error. It is occurring because we’re putting 2 schematics under 1 cell name 2. Instance parts: (1) vdd, 3 gnd’s, (2) vdc’s, (1) 10pF capacitor, and your NAND gate, to create the following schematic: o Tip: You can copy and paste most of this stuff from your other test bench: o Select everything in your old schematic o Press “c” and point at the selected components o Then in your new schematic, point where you want the copy to be put o Add Wire Names: IN and OUT (do NOT use A, B, OUT as before) o Set the DC voltage of the “VDC” attached to both inputs of the NAND gate, to 0 Why have we tied the inputs together??? -if you look at the schematic, tie the inputs together in your mind, and you’ll see we’ve just turned our NAND gate into an inverter! -we’re now going to size the pmos’ and nmos’ just as we did in lab2 to obtain a midpoint on the VTC graph3. Click on the NAND symbol, press the letter “X” to “descend” into the schematic view o Make sure you use capitol X o Set the Width of both PMOS transistors to a variable named: w_p o Set the Width of both NMOS transistors to a variable named: w_n o Save the schematic o Press the letter “b” to “return” to the test bench view 4. Open up the simulator, use Spectre, and create a “DC” analysis o Choose the sweep variable to be a “Component Parameter” and select the DC input to your NAND gate as the component to be varied, from 0 to 5 volts as follows: o If you have forgotten these steps, see Lab 2 for detailed instructions o Your components may have different names, so don’t just fill in the form, select from the schematic 5. Copy the “Variables” you setup from the cell view: o From the menu, choose: Variables->Copy From Cell View o Give them default