EE 462: Laboratory Assignment 7 Using NMOS Transistors to Build Logic Gates by Dr. A.V. Radun Dr. K.D. Donohue (10/13/03) Department of Electrical and Computer Engineering University of Kentucky Lexington, KY 40506 Laboratory # 7 Pre-lab due at lab sessions October 21, 22, and 23. Lab due at lab sessions October 28, 29, and 30. I. Instructional Objectives • Analyze the MOSFET transistors as digital devices • Measure the effect of stray capacitance in MOSET transistor digital circuits • Know the nomenclature of digital circuits See Horenstein 5.2.2, 6.1.2, 6.4.1, and 6.4.2 II. Background This lab deals with the digital (nonlinear or large signal) operation of MOSFET transistors. The operation of a MOSFET can be understood by plotting the load line (Kirchhoff’s voltage law for the drain circuit) on the characteristic curves of the MOSFET. The MOSFET’s drain-to-source voltage can never be greater than the VDD supply voltage (cutoff region ID = 0) or less than zero (triode region). Digital applications call for the device to be operated at the extreme ends of the transfer characteristic (load line), designated logic 1 for high drain-to-source voltage (cutoff region, ID =0, VDS = VDD) and logic 0 for low output voltage (triode region, VDS = small value, ID = its maximum value). The region between these two extremes is called the analog region. This region is undefined for digital operation and is traversed only when the output changes between its logic 1 and logic 0 states. This lab uses the MOSFET transistor in common logic circuits. The simplest logic circuit uses the MOSFET in the common source configuration to perform the logic negate function. This device is referred to as an inverter. The configuration for such an inverter is shown below in Fig. 1. Figure 2 shows the circuit’s transfer characteristic, truth table, and truth table in terms of voltage levels. Ideally, the transfer function’s transition from a digital high value to a digital low value will be a vertical line at VDD / 2 and VOL will be zero. The sharpness of this transition depends on the Kp of the MOSFET, where more vertical transitions result from a higher Kp MOSFET.VDD Vin D G S Vout + - RD RG + - Load Vin Vout VOLVOH = VDDVf = Vtr VIH = VDD Input Vin VoutOutput 0 0 1 1 VIL = VOL VOH = VDD VIH = VDD VOL Fig.1. Logic Inverter Circuit Fig. 2. Transfer characteristic and truth table for inverter It is generally not desirable to use very high Kp MOSFETs in digital circuits, since these devices are physically large and this limits the number of transistors that can be placed on a single chip. The single chip MOSFET used in the lab has an unusually large Kp and is larger than normal digital MOSFETs. The highest output voltage produced by the inverter occurs when its input is a logic zero ( VVin 0≈ ) and its output (with no load) represents logic 1. This voltage is given the symbol VOH. If the inverter is fed an input voltage equal to VOH, the result is a low output voltage, representing logic 0. This voltage is given the symbol VOL. In practice, many effects, including output loading, noise, power supply fluctuations, and component variations will cause extraneous voltage components to be added to or subtracted from the otherwise perfect logic signals VOH and VOL. Thus, the input voltage levels the logic circuits must interpret as logic 1 and 0 are usually extended slightly into the analog region to include voltages lying slightly below VOH and slightly above VOL. For the case where the output of the logic inverter is 1, the drain current is zero and thus Vin < Vtr. The case for a logic inverter output of 0 is more complex since the MOSFET is operating in the triode region. Recall in the triode region for VGS=VIH: () ()⎟⎟⎠⎞⎜⎜⎝⎛−−=⎟⎟⎠⎞⎜⎜⎝⎛−−=2222DSDStrIHDSDStrGSDVVVVKpVVVVKpI (1) When VDS is small the VDS2 term can be neglected (this is the same as expanding the function ID(VGS,VDS) in a Taylor series and keeping only the linear terms) and the drain current can be approximated as: ()onDSDStrIHDrVVVVKpI =−= where ()trIHonVVKpr−=1 (2) Thus the circuit in Fig. 1 can be approximated with the circuit in Fig 3 when the output is logic 1 and the circuit in Fig. 4 when the output is a logic zero.VDD D S Vout + - RD Load VDD D SVout + - RD Load ron Fig. 3. Simplified logic inverter circuit for logic output 1 state. Fig. 4. Simplified logic inverter circuit for logic output 0 state. III. Pre-Laboratory Exercise You are to design a logic inverter using the ZVN3306A with Kp = 2K= 0.1233 A / V2, and Vtr = 1.8 V (or 2N7000 N-channel MOSFET with Kp = 2K = 0.225 A / V2, and Vtr = 2.1 V). Or, you can use the values you measured in the last lab if you think they are reasonable. The drain voltage supply is 5Vdc and the drain current with a logic zero output is to be approximately 1 mA. 1. For the MOSFET inverter described above, find VIL , which is he largest value that Vin can have when the MOSFET is in cutoff mode, with Vout = VDD and Vin corresponding to logic 0. What is ID in this case? Does the result depend on RD? 2. Estimate the MOSFET’s channel resistance ron for the ZVN3306A/2N7000 (VGS = 5V). Determine VOL when the drain current is 1mA. 3. What must the logic inverter’s drain resistor value be? 4. Using your drain resistor from part 3) draw the circuits load line and at least one device characteristic curve, the one for ID = 1mA. For the MOSFET in saturation mode, determine the gate to source voltage so that the drain current equals 1mA. For this gate to source voltage, what value of drain-to-source voltage is at the boundary between the saturated and triode regions of MOSFET operation? 5. What are VOH and VOL for the MOSFET inverter with no load, a 10kΩ load, and a general MOSFET inverter load Rload? 6. What is the drain current for logic 1 out and logic 0 out with no load (Rload = infinite), a 10kΩ load, and a general MOSFET inverter load Rload? 7. What is the power from the VDD supply and Vin source for logic 1 out and logic 0 out? 8. Simulate your inverter design using SPICE. Use the level 1 model of the MOSFET with the values of Kp and Vtr for the ZVN3306A/2N7000 listed above (or the values you measured last lab) and leaving all of the other MOSFET parameters at their default values. Make your own MOSFET model. Do not use the ZVN3306A/2N7000 library model. Make your input a