EE 462: Laboratory Assignment 6 Biasing of Transistors: N- channel MOSFET by Dr. A.V. Radun and Dr. K.D. Donohue (10/2/03) Department of Electrical and Computer Engineering University of Kentucky Lexington, KY 40506 Laboratory # 6 Pre-lab due at lab sessions October 14, 15, and 16. Lab due at lab sessions October 21, 22, and 23. I. Instructional Objectives • Analyze the metal oxide semiconductor (MOS) field effect transistor (FET) (MOSFET) using a DC load line • Design a circuit to set a DC operating point for a MOSFET • Measure the operating points in a DC biased FET circuit See Horenstein 5.2, 7.3.1, and 7.3.3 II. Background Transistors are nonlinear devices, but over certain operating regions they can be approximated with linear models. To ensure a transistor operates in its linear region, a DC level is added to its input signal. The design of this DC level is referred to as biasing the transistor, and the DC values of the transistor's currents and voltages are referred to as the transistor’s DC operating point, its bias point, or its quiescent operating point. Once a transistor is biased in its linear region, currents and voltages in a neighborhood around the bias point will vary linearly (approximately). It is assumed that the variation of the transistor's input signal and the transistor's currents and voltages are small enough that they do not move the system into nonlinear regions of operation (triode region or cutoff). The simplest common source MOSFET amplifier biasing scheme is shown in Fig. 1. Since only the DC operating point is of interest right now, the time varying part of the input signal is omitted. The actual signal would be an AC signal added to the VGG (Gate to Ground DC signal). The transfer characteristic (output as a function of the input) for this circuit can be derived. Apply KVL in Fig. 1 to obtain: DDDDoutIRVV −=, (1)then using a relationship between ID and the gate voltage VGG when the MOSFET is in the saturated (forward active) region, Eq. (1) becomes: ()22trGGpDDDoutVVKRVV −−= where KKp=2 (Horrenstein uses K and Spice uses Kp), (2) and Vtr is the threshold voltage between the cutoff and triode operation region. The operating points of VGG and Vout are the DC or quiescent values at the input and output, respectively. Ideally, for a given VGG, Vout should not vary if the temperature varies or if different transistors of the same type are used. Unfortunately the MOSFET's transconductance parameter Kp cannot be controlled well during manufacturing. In addition, Kp also varies with temperature. For example, the 2N7000 MOSFET transistor’s Kp can vary by more than 3.2 to 1. Note that Kp is not directly specified in the data sheet but rather the transconductance gm is specified. The relationship between the MOSFET’s transconductance gm and Kp will be addressed in future labs. Since Kp varies significantly, a circuit biased correctly for one transistor may not be biased correctly for another transistor of the same manufacture and part number. Therefore, a more robust biasing scheme than the one shown in Fig. 1 is needed, such that the MOSFET's quiescent operating point is less sensitive to changes in Kp. Insensitivity of the MOSFET's quiescent operating point can be achieved by adding a resistor RS into the source branch of the circuit as shown in the Fig. 2. An analysis this new circuit, similar to before, results in the following equations: SDGSGGRIVV += (3) VDD VGG D GS Vout+ -RD RG ID + - Fig. 1 Basic common source amplifier biasing.()()()()22222 2222DISRpKDItrVGGVSRpKtrVGGVpKtrVSRDIGGVpKtrVGSVpKDI+−−−=−−=−= (4) ()()0222222=−+⎟⎟⎠⎞⎜⎜⎝⎛+−−StrGGDpSStrGGDRVVIKRRVVI (5) VDDVGG D GS Vout+ - RD RG RS+ - ID Fig. 2 Basic common source amplifier with reduced Kp sensitivity. Note that when RS goes to zero (multiply by 2SR and let RS go to zero), Eq. (5) simplifies to: ()22trVGSVpKDI −= (6) which is the same relationship for the circuit in Fig. 1. (Why should this be expected?) One the other hand, if the RS is large (relative to 2), then Eq. (5) is approximated by: ()()02222=−+−−SSRtrVGGVDIRtrVGGVDI (7) Notice that in Eq. (5), Kp only appeared in one term, whose effect was minimized (relative to the other terms) by a large RS value. The quadratic in Eq. (7) is a perfect square and can be rewritten as:()02=⎟⎟⎠⎞⎜⎜⎝⎛−−SRtrVGGVDI or ()SRtrVGGVDI−= (8) Thus if RSKp is large, ID is practically independent of Kp as desired. The general solution for ID valid for any Kp is: () () ()2212122SRtrVGGVpKSRSRtrVGGVpKSRSRtrVGGVDI−−⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛+−−⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛+−= (9) From Eq. (9), the approximation of Eq. (8) can also be obtained by letting Rs get large. This circuit of Fig. 2 is still not as efficient as it can be because it requires two power supplies: one for VGG and another for VDD. The circuit in Fig. 3 remedies this. The Thévenin equivalent for the circuit consisting of VDD, R1, and R2 in Fig. 3 gives the biasing circuit in Fig. 2 where VGG = Vth and RG = Rth. With these Thévenin equivalents substituted into the circuit, the circuit is identical to the circuit in Fig. 2 with the exception that the bias voltage VGG is now dependent on VDD. The VGG voltage is now controlled by the proper choice of R1 and R2. This eliminates the need for a separate power supply to control VGG. The gate current into the MOSFET is zero so the gate voltage is thus determined by only VDD and the R1, R2 voltage divider. VDD D G S Vout + - RD R 2 RS R 1 +-ID Fig. 3 Basic common source amplifier biasing with reduced Kp sensitivity and employing a single DC voltage. The DC Operating point of this circuit is stable for two primary reasons:• The gate voltage is determined by only the voltage divider R1 and R2 , since insignificant current flows into the transistor gate, and is therefore independent of the transistor parameters (especially Kp). • The source resistor RS stabilizes the DC operating point through negative feedback. If Kp increases for any reason, such as temperature change, the subsequent rise in source current will increase the voltage drop across RS, thereby increasing VS and thus decreasing VGS (since the gate voltage is a constant). The decrease in VGS will counteract the attempted increase in IS. III. Pre-Laboratory Exercise The MOSFET you