Electronic Circuits Laboratory EE462G Lab #6Logic Device NomenclatureFET Operation as a Logic DeviceTransfer CharacteristicSlide 5Truth TableTransition Between StatesTransition Low to HighTransition High to LowSPICE AnalysisSPICE ResultsSlide 12Kevin D. Donohue, University of Kentucky1Electronic Circuits LaboratoryEE462GLab #6Using NMOS Transistors to Build Logic GatesKevin D. Donohue, University of Kentucky2Logic Device Nomenclature 5-Volt Positive logic: Logic gate circuitry where a 5V level corresponds to logic 1 and 0V level corresponds to logic 0.Truth Table: Input-output description of gate in terms of logic symbols.VIL: Highest input voltage guaranteed to be accepted as a logic 0.VIH: Lowest input voltage guaranteed to be accepted as a logic 1.VOL: Highest logic-0 output voltage produced (given inputs are consistent with VIL and VIH).VOH: Lowest logic-1 output voltage produced (given inputs are consistent with VIL and VIH).Kevin D. Donohue, University of Kentucky3FET Operation as a Logic DeviceInput values will change between 0 volts (VGS < Vtr) and 5 volts (VGS> VDS+Vtr). Thus, the NMOS transistor will operate primarily in the cutoff and triode regions. The circuit below represents a logic inverter.Three Regions of Operation:Cutoff region (VGS  Vtr)Triode region (VDS  VGS - Vtr )Saturation (VGS - Vtr  VDS ) VDD Vin D G S Vout + - RD RG + - LoadKevin D. Donohue, University of Kentucky4Transfer CharacteristicObtain relationship between Vin to Vout in cutoff region.0 DtrGSinIVVVoutDSDDDSDDDDVVVVIRV   VDD Vin D G S Vout + - RD RG + - Load IDVinVoutVtrVDD=VOHWhat would VIL be in this case?Kevin D. Donohue, University of Kentucky5Transfer CharacteristicObtain relationship between Vin to Vout in Triode region. onDSDStrGSDtrDSGSinrVVVVKpIVVVV  OLonDDDoutonDDSDDDSDDDDVrRVVrRVVVIRV   11 VDD Vin D G S Vout + - RD RG + - Load ID trGSonVVKpr1whereVinVoutVtrVDD=VOHVOLWhat would VIH be in this case?Kevin D. Donohue, University of Kentucky6Truth TableThe truth table with logic input-output relationships are shown below:VinVoutVtrVDD=VOHVOLInputVinVoutOutput0011VIL < VtrVOH VDDVIH > VtrOLonDDDVrRV1Kevin D. Donohue, University of Kentucky7The stray capacitance in the NMOS device limits the speed of the transition between states of the inverter.Capacitive effects between the drain and source, and gate and source create delays (propagation delay) between input and output transitions, and nonzero rise times and fall times of the output transitions.These quantities are defined below:Transition Between States t Vout Vin t tfdelay trdelay trise tfall 50% 50% 50% 50% 90% 10% 90% 10% turn off turn on Propagation delay is taken as the average between the 2 edge delays2delaydelayPDtftrtKevin D. Donohue, University of Kentucky8Transition Low to HighThe equivalent circuit below represents the NMOS inverter going into a logic 1 output state.Circuit equations are: RDRONCVDDVGS <Vtr+Vout-outDoutDDVCRVVOLoutVV )(0CRtVVVtVDOLDDDDoutexp)()(What critical parameter affects the rise time?What effects would VDD have on the rise time?Kevin D. Donohue, University of Kentucky9Transition High to LowThe equivalent circuit below represents the NMOS inverter going into a logic 0 output state.Circuit equations are:RDRONCVDDVGS >Vtr+Vout-outDONONDoutDDDONONVCRRRRVVRRRDONONDDOLOHoutRRRVVVV 0 )(CRRRRtVVVtVDONDONOHOLOLoutexp)()(What critical parameter affects the fall time?What effects would VDD have on the fall time (note this ends in the triode region)?Kevin D. Donohue, University of Kentucky10SPICE AnalysisThe logic circuit can be analyzed in SPICE. For this lab use the MOSFET (Level 1 NMOS) component model. This is a generic model where parameters such as Kp and Vtr can be set. Stray capacitance values can also be set; however, this lab does not request this.The transient simulation can be run, using V2 as VDD and V1 as a square wave (pulse setting in SPICE). The input and output voltages can be observed simultaneously.M1M1 V10R1 10K R2 5K V25IVm1IVm2Kevin D. Donohue, University of Kentucky11SPICE ResultsUsing a 10kHz square wave input, Kp=.225 and Vtr = 2.1:TIME +35.560u V(IVM1) +1.533m V(IVM2) +5.000 D(TIME) 0.0D(V(IVM1)) 0.0Cirex-Transient-5Time (s)(V)0.0+2.000+4.000+6.0000.0 +20.000u +40.000u +60.000u +80.000u +100.000u +120.000uKevin D. Donohue, University of Kentucky12SPICE ResultsUsing a 10kHz square wave input, Kp=.225 and Vtr = 2.1 and Drain-Body and Source-Body capacitance of 1nF each:TIME -1.000 V(IVM1) -1.000 V(IVM2) -1.000 D(TIME) -1.000D(V(IVM2)) -1.002Cirex-Transient-6Time (s)(V)0.0+2.000+4.000+6.0000.0 +20.000u +40.000u +60.000u +80.000u +100.000u