DOC PREVIEW
UMD ENEE 416 - Aligned Wafer Level Bonding

This preview shows page 1-2-3-4 out of 12 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 12 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 12 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 12 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 12 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 12 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Aligned Wafer LevelAligned Wafer LevelBondingBondingBrian Brian DrewryDrewryENEE416ENEE416Fall 2009Fall 2009What is What is Aligned Wafer Level Bonding?Aligned Wafer Level Bonding?Aligned Wafer Level Bonding can be described as process thatAligned Wafer Level Bonding can be described as process thatallows stacking two or more processed wafers together involving,allows stacking two or more processed wafers together involving,““the application of intermediary layer, wafer alignment and bondingthe application of intermediary layer, wafer alignment and bonding””(Lindner, 1439).(Lindner, 1439).Benefits of Aligned Wafer BondingBenefits of Aligned Wafer BondingThe benefits of device stacking are:The benefits of device stacking are:““size reductionsize reductionincrease in increase in ““silicon efficiencysilicon efficiencyreduction in signal delayreduction in signal delayreduced parasiticreduced parasiticdecrease in power consumptiondecrease in power consumptionincrease in speedincrease in speedincrease in number of neighboring devicesincrease in number of neighboring devicesextension of bandwidthextension of bandwidth”” (Linder, 1439). (Linder, 1439).Intermediate Layers for WaferIntermediate Layers for WaferBondingBondingAn intermediate layer is necessary when bonding two wafers or substratesin wafer level alignment.There are seven different types of intermediate layers, “available for 3-Dinterconnection technology and wafer level packaging: Solder alloys: requires low temperature and low forceGold to gold wafer bonding: requiring high temperature and high forceCopper to copper wafer bonding: requiring high temperature and high forceAluminum to aluminum wafer bonding: requiring reduced atmosphere(forming gas), high temperature and high forceAnodic bonding: requiring high temperature, high vacuum, high voltageSilicon direct bonding (SDB): requires ultra clean bonding environmentPolymer bonding: requiring low temperature, low force, high vacuum”(Linder,1440).The various mechanical properties of the surface is vital to the viability ofthe process viscosity, thermal mismatch and fragility of the bondingelements should be considered.Infrared Alignment:Infrared Alignment:One of the first methods used inOne of the first methods used inwafer alignment was Infraredwafer alignment was InfraredAlignment.Alignment.This method utilizes the infraredThis method utilizes the infraredlight for the alignment process.light for the alignment process.Silicon is, Silicon is, ““transparent in thetransparent in theinfrared spectrum, one can viewinfrared spectrum, one can viewand align both wafers to eachand align both wafers to eachotherother”” ( (MirzaMirza, 677), 677)The limitations of using infraredThe limitations of using infraredimaging is diffraction, imaging is diffraction, ““alignmentalignmenterrors of +/- 5umerrors of +/- 5um””Transparency of the wafers mayTransparency of the wafers maynot be entirely clear due tonot be entirely clear due tocomposition of the wafer,composition of the wafer,particularly metal components thatparticularly metal components thatdo not allow infrared light passdo not allow infrared light passthrough (through (MirzaMirza, 677)., 677).Through Wafer Via HolesThrough Wafer Via HolesEtches an hole entirelyEtches an hole entirelythrough the first wafer tothrough the first wafer toview the second wafer forview the second wafer forthe alignment processthe alignment processshown in figure 3.shown in figure 3.This process This process ““requiresrequiresprecision registration ofprecision registration ofthe backside via holethe backside via holemask to the front side ofmask to the front side ofthe the waferwafer””(Mirza(Mirza, 677)., 677).This method is useful inThis method is useful inMEMS applicationsMEMS applicationswhere the thickness iswhere the thickness isseveral microns.several microns.Wafer Backside AlignmentWafer Backside AlignmentUtilizes alignment keys on theUtilizes alignment keys on thebackside of the first wafer whichbackside of the first wafer whichare then aligned to the front sideare then aligned to the front sidealignment marks of the secondalignment marks of the secondwafer, shown in figure 4.wafer, shown in figure 4.This method is, This method is, ““a standard fora standard forMEMS wafer bonding.MEMS wafer bonding.Requires precision registrationRequires precision registrationprecision registration of theprecision registration of thebackside alignment keys to thebackside alignment keys to thefront side marks and exactfront side marks and exactalignment of the wafers.alignment of the wafers.The registration of alignment keysThe registration of alignment keysand the aligning of both wafers,and the aligning of both wafers,““each introduce errors of the ordereach introduce errors of the orderof 1 umof 1 um”” ( (MirzaMirza, 678)., 678).Is acceptable for MEMSIs acceptable for MEMSapplications in the order of two orapplications in the order of two ormore microns.more microns.Figure 4: Wafer to wafer alignment using WaferBackside Alignment Keys.Face to Face Alignment: UsingFace to Face Alignment: UsingSmartViewSmartViewUtilizes two microscopes forUtilizes two microscopes foralignment, one above and onealignment, one above and onebelow the wafer stack.below the wafer stack.The two microscopes, The two microscopes, ““systemsystemfocuses on a common axisfocuses on a common axiscalibrated for each alignment.calibrated for each alignment.Each microscope objectiveEach microscope objectiveobserves one alignment key onobserves one alignment key onthe surface of the waferthe surface of the wafer””Each microscope digitally storesEach microscope digitally storesthe alignment key of the farthestthe alignment key of the farthestwafer then aligns the waferswafer then aligns the wafersaccording to the digital alignmentaccording to the digital alignmentkeys (keys (DragoiDragoi, 426)., 426).Both wafer alignment stages,Both wafer alignment stages,““uses encoded stage motors thatuses encoded stage motors thatallow X,Y movements of 0.1allow X,Y movements of 0.1micronmicron”” ( (MirzaMirza, 679)., 679).Face to Face Alignment: UsingFace to Face Alignment: UsingSmartViewSmartViewBoth wafer alignment stages, Both wafer alignment stages, ““uses encoded stageuses encoded stagemotors that allow X,Y movements of 0.1 micronmotors that allow X,Y movements of 0.1 micron”” (


View Full Document

UMD ENEE 416 - Aligned Wafer Level Bonding

Download Aligned Wafer Level Bonding
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Aligned Wafer Level Bonding and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Aligned Wafer Level Bonding 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?