CS 105 Tour of the Black Holes of Computing Virtual Memory Topics VM1 Motivations for VM Address translation Accelerating translation with TLBs Motivations for Virtual Memory Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory Each process with its own address space Only active code and data is actually in memory Allocate more memory to process as needed Provide Protection One process can t interfere with another Because they operate in different address spaces User process cannot access privileged information Different sections of address spaces have different permissions 2 CS 105 Motivation 1 DRAM As Cache for Disk Full address space is quite large 32 bit addresses 4 000 000 000 4 billion bytes 64 bit addresses 16 000 000 000 000 000 000 16 quintillion bytes Disk storage is 300X cheaper than DRAM storage 250 GB of DRAM 25 000 667 MHz late 2006 prices 250 GB of disk 55 To access large amounts of data in a cost effective manner the bulk of the data must be stored on disk 4 MB 250 SRAM 3 1GB 110 DRAM 250 GB 55 Disk CS 105 Levels in Memory Hierarchy cache CPU CPU regs regs Register size speed Mbyte line size 32 B 0 3 ns 8B 8B C a c h e 32 B Cache 32 KB 4MB 2 ns 65 MB 32 B virtual memory Memory Memory Memory 2048 MB 7 5 ns 0 10 MB 4 KB 4 KB disk disk Disk Memory 250 GB 8 ms 0 0002 MB larger slower cheaper 4 CS 105 DRAM vs SRAM as a Cache DRAM vs disk is more extreme than SRAM vs DRAM Access latencies DRAM 10X slower than SRAM Disk 100 000X slower than DRAM Importance of exploiting spatial locality First byte is 100 000X slower than successive bytes on disk vs 4X improvement for page mode vs regular accesses to DRAM Bottom line Design decisions made for DRAM caches driven by enormous cost of misses SRAM 5 DRAM Disk CS 105 Impact of Properties on Design If DRAM was to be organized similar to an SRAM cache how would we set the following design parameters Line size Large since disk better at transferring large blocks Associativity High to mimimize miss rate Write through or write back Write back since can t afford to perform small writes to disk What would the impact of these choices be on miss rate Extremely low 1 hit time Must match cache DRAM performance miss latency Very high 20ms tag storage overhead Low relative to block size 6 CS 105 Locating an Object in a Cache SRAM Cache Tag stored with cache line Maps from cache block to memory blocks From cached to uncached form Save a few bits by only storing tag of data blocks in cache No tag for block not in cache Hardware retrieves information Can quickly match against multiple tags Cache Object Name X X Tag Data 0 D 243 1 X J 17 105 N 1 7 CS 105 Locating an Object in a Cache DRAM Cache Each allocated page of virtual memory has entry in page table Mapping from virtual pages to physical pages From uncached form to cached form Page table entry tag even if page not in memory Specifies disk address Only way to indicate where to find page OS retrieves information Page Table Cache Location Data Object Name D 0 0 243 X J On Disk 1 17 105 8 X 1 N 1 CS 105 A System with Physical Memory Only Examples Most Cray machines early PCs nearly all embedded systems etc Memory Physical Addresses 0 1 CPU N 1 9 Addresses generated by the CPU correspond directly to bytes in physical memory CS 105 A System with Virtual Memory Examples Memory Workstations servers modern PCs etc Virtual Addresses 0 1 Page Table 0 1 Physical Addresses CPU P 1 N 1 Disk Address Translation Hardware converts virtual addresses to physical addresses via OS managed lookup table page table 10 CS 105 Page Faults like Cache Misses What if an object is on disk rather than in memory Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory VM and Multiprogramming are symbiotic Current process suspends others can resume OS has full control over placement etc Before fault Virtual Addresses Page Table Physical Addresses CPU Memory Page Table Virtual Addresses Physical Addresses CPU Disk 11 After fault Memory Disk CS 105 Servicing a Page Fault Processor Signals Controller Read block of length P starting at disk address X and store starting at memory address Y Read Occurs Direct Memory Access DMA Under control of I O controller I O Controller Signals Completion Interrupt processor OS resumes suspended process 12 1 Initiate Block Read Processor Processor Reg 3 Read Done Cache Cache Memory I O Memory I Obus bus 2 DMA Transfer I O I O controller controller Memory Memory disk Disk disk Disk CS 105 Motivation 2 Memory Mgmt Multiple processes can reside in physical memory How do we resolve address conflicts What if two processes access something at the same address kernel virtual memory stack esp Memory mapped region for shared libraries Linux x86 process memory image 13 memory invisible to user code runtime heap via malloc 0 the brk ptr uninitialized data bss initialized data data program text text forbidden CS 105 Solution Separate Virtual Address Spaces Virtual and physical address spaces divided into equal sized blocks Blocks are called pages both virtual and physical Each process has its own virtual address space Operating system controls how virtual pages as assigned to physical memory Virtual Address Space for Process 1 Virtual Address Space for Process 2 14 0 Address Translation 0 VP 1 VP 2 PP 2 N 1 PP 7 0 VP 1 VP 2 N 1 Physical Address Space DRAM e g read only library code PP 10 M 1 CS 105 Contrast Macintosh Memory Model MAC OS 1 9 Does not use traditional virtual memory P1 Pointer Table Process P1 Shared Address Space A B Handles Process P2 P2 Pointer Table C D E All program objects accessed through handles Indirect reference through pointer table Objects stored in shared global address space 15 CS 105 Macintosh Memory Management Allocation Deallocation Similar to free list management of malloc free Compaction Can move any object and just update the unique pointer in pointer table P1 Pointer Table Shared Address Space B Process P1 A Handles P2 Pointer Table Process P2 C D 16 E CS 105 Mac vs VM Based Memory Management Allocating deallocating and moving memory Can be accomplished by both techniques Block sizes Mac variable sized May be very small or very large VM fixed size Size is equal to one page 4KB on x86 Linux systems Allocating
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