CS 105 Tour of the Black Holes of Computing P6 Linux Memory System Topics P6 address translation Linux memory management Linux page fault handling Memory mapping Intel P6 Internal designation for successor to Pentium Pentium had internal designation P5 Fundamentally different from Pentium Out of order superscalar operation Designed to handle server applications Requires high performance memory system Resulting processors PentiumPro 1996 Pentium II 1997 Incorporated MMX instructions Special instructions for parallel processing L2 cache on same chip Pentium III 1999 Incorporated Streaming SIMD Extensions SSE More instructions for parallel processing 2 CS 105 P6 Memory System external system bus e g PCI 3 L1 i cache 32 entries 8 sets data TLB cache bus bus interface unit 4 way set associative inst TLB L2 cache processor package 4 KB page size L1 L2 and TLBs DRAM instruction fetch unit 32 bit address space inst TLB data TLB L1 d cache 64 entries 16 sets L1 i cache and d cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB 2 MB CS 105 Review of Abbreviations Symbols Components of the virtual address VA VPO virtual page offset VPN virtual page number TLBI TLB index TLBT TLB tag Components of the physical address PA PPO physical page offset same as VPO PPN physical page number CO byte offset within cache line CI cache index CT cache tag 4 CS 105 Overview of P6 Address Translation 32 result CPU 20 VPN 12 virtual address VA VPO TLB 16 sets 4 entries set 10 10 VPN1 VPN2 PDE PDBR 5 PTE Page tables L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 and DRAM L1 128 sets 4 lines set TLB hit 20 PPN 20 CT 12 PPO 7 5 CI CO physical address PA CS 105 P6 2 Level Page Table Structure Page directory 1024 4 byte page directory entries PDEs that point to page tables One page directory per process Page directory must be in memory when its process is running Always pointed to by PDBR Page tables 6 Up to 1024 page tables 1024 4 byte page table entries PTEs that point to pages Page tables can be paged in and out page directory 1024 PDEs 1024 PTEs 1024 PTEs 1024 PTEs CS 105 P6 Page Table Entry PTE 31 12 11 Page physical base address 9 Avail 8 7 6 5 G 0 D A 4 3 2 1 0 CD WT U S R W P 1 Page base address 20 most significant bits of physical page address forces pages to be 4 KB aligned Avail available for system programmers G global page don t evict from TLB on task switch D dirty set by MMU on writes A accessed set by MMU on reads and writes cleared by software CD cache disabled 0 or enabled 1 for this page WT write through or write back cache policy for this page U S user supervisor R W read write P page is present in physical memory 1 or not 0 31 1 Available for OS page location in secondary storage 7 0 P 0 CS 105 P6 Page Directory Entry PDE 31 12 11 Page table physical base addr 9 Avail 8 7 6 5 G PS 0 A 4 3 2 1 0 CD WT U S R W P 1 Page table physical base address 20 most significant bits of physical page table address forces page tables to be 4KB aligned Avail These bits available for system programmers G global page don t evict from TLB on task switch PS page size 4K 0 or 4M 1 A accessed set by MMU on reads and writes cleared by software CD cache disabled 1 or enabled 0 for this page table WT write through or write back cache policy for this page table U S user or supervisor mode access R W read only or read write access P page table is present in memory 1 or not 0 31 1 Available for OS page table location in secondary storage 8 0 P 0 CS 105 How P6 Page Tables Map Virtual Addresses to Physical Ones 10 VPN1 10 VPN2 word offset into page directory 12 VPO word offset into page table page directory PDE physical address of page table base if P 1 20 PPN 9 word offset into physical and virtual page page table PTE PDBR physical address of page directory Virtual address physical address of page base if P 1 12 PPO Physical address CS 105 Representation of Virtual Address Space PT 3 Page Directory P 1 M 1 P 1 M 1 P 0 M 0 P 0 M 1 PT 2 PT 0 P 1 M 1 P 0 M 0 P 1 M 1 P 0 M 1 P 1 M 1 P 0 M 0 P 1 M 1 P 0 M 1 P 0 M 1 P 0 M 1 P 0 M 0 P 0 M 0 Simplified Example 16 page virtual address space Flags 10 P Is entry in physical memory M Has this part of VA space been mapped Page 15 Page 14 Page 13 Page 12 Page 11 Page 10 Page 9 Page 8 Page 7 Page 6 Page 5 Page 4 Mem Addr Page 3 Disk Addr Page 2 In Mem Page 1 Page 0 On Disk Unmapped CS 105 P6 TLB Translation 32 result CPU 20 VPN 12 virtual address VA VPO TLB 16 sets 4 entries set 10 10 VPN1 VPN2 PDE PDBR 11 PTE Page tables L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 and DRAM L1 128 sets 4 lines set TLB hit 20 PPN 20 CT 12 PPO 7 5 CI CO physical address PA CS 105 P6 TLB TLB entry not all documented so this is speculative 32 16 1 1 PDE PTE Tag PD V V indicates a valid 1 or invalid 0 TLB entry PD is this entry a PDE 1 or a PTE 0 Tag disambiguates entries cached in the same set PDE PTE page directory or page table entry Structure of the data TLB 12 16 sets 4 entries set entry entry entry entry entry entry entry entry entry entry entry entry entry entry set 0 set 1 set 2 entry entry set 15 CS 105 Translating with the P6 TLB 1 Partition VPN into TLBT and TLBI CPU 20 VPN 16 4 TLBT TLBI TLB miss 1 2 PDE page table translation 13 2 Is the PTE for VPN cached in set TLBI 12 virtual address VPO TLB PTE hit 3 20 PPN 12 PPO physical address 4 3 Yes then build physical address 4 No then read PTE and PDE if not cached from memory and build physical address CS 105 P6 page table translation 32 result CPU 20 VPN 12 virtual address VA VPO TLB 16 sets 4 entries set 10 10 VPN1 VPN2 PDE PDBR 14 PTE Page tables L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 and DRAM L1 128 sets 4 lines set TLB hit 20 PPN 20 CT 12 PPO 7 5 CI CO …
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