The Memory HierarchyRandom-Access Memory (RAM)Non-Volatile RAM (NVRAM)Conventional DRAM OrganizationReading DRAM Supercell (2,1)Slide 6Memory ModulesTypical Bus Structure Connecting CPU and MemoryMemory Read Transaction (1)Memory Read Transaction (2)Memory Read Transaction (3)Memory Write Transaction (1)Memory Write Transaction (2)Memory Write Transaction (3)Disk GeometryDisk Geometry (Muliple-Platter View)Disk Operation (Single-Platter View)Disk Operation (Multi-Platter View)Disk Access TimeDisk Access Time ExampleLogical Disk BlocksI/O BusReading a Disk Sector (1)Reading a Disk Sector (2)Reading a Disk Sector (3)Storage TrendsCPU Clock RatesThe CPU-Memory GapLocalityLocality ExampleSlide 31Slide 32Memory HierarchiesAn Example Memory HierarchyCachesCaching in a Memory HierarchyGeneral Caching ConceptsGeneral Caching ConceptsExamples of Caching in the HierarchyThe Memory HierarchyThe Memory HierarchyTopicsTopicsStorage technologies and trendsLocality of referenceCaching in the memory hierarchyCS 105Tour of the Black Holes of Computing– 2 –CS 105Random-Access Memory (RAM)Random-Access Memory (RAM)Key featuresKey featuresRAM is packaged as a chipBasic storage unit is a cell (one bit per cell)Multiple RAM chips form a memoryStatic RAM (Static RAM (SRAMSRAM))Each cell stores bit with a six-transistor circuitRetains value indefinitely, as long as it is kept poweredRelatively insensitive to disturbances such as electrical noiseFaster and more expensive than DRAMDynamic RAM (Dynamic RAM (DRAMDRAM))Each cell stores bit with a capacitor and transistorValue must be refreshed every 10-100 msSensitive to disturbancesSlower and cheaper than SRAM– 3 –CS 105Non-Volatile RAM (NVRAM)Non-Volatile RAM (NVRAM)Key Feature: Keeps data when power lostKey Feature: Keeps data when power lostSeveral typesMost important is NAND flashOngoing R&DNAND flashNAND flashReading similar to DRAM (though somewhat slower)Writing packed with restrictions:Can’t change existing dataMust erase in large blocks (e.g., 64K)Block dies after about 100K erasesWriting slower than reading (mostly due to erase cost)Chips often packaged with Flash Translation Layer (FTL)Spreads out writes (“wear leveling”)Makes chip appear like disk drive– 4 –CS 105Conventional DRAM OrganizationConventional DRAM Organizationd x w DRAM:d x w DRAM:dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)– 5 –CS 105Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 1(a): Row address strobe (Step 1(a): Row address strobe (RASRAS) selects row 2) selects row 2colsrowsRAS = 201 2 3012internal row buffer16 x 8 DRAM chip3addrdata2/8/memorycontrollerStep 1(b): Row 2 copied from DRAM array to row bufferStep 1(b): Row 2 copied from DRAM array to row buffer– 6 –CS 105Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 2(a): Column access strobe (Step 2(a): Column access strobe (CASCAS) selects column 1) selects column 1colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerStep 2(b): Supercell (2,1) copied from buffer to data lines, Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to CPUand eventually back to CPUsupercell (2,1)supercell (2,1)To CPU– 7 –CS 105Memory ModulesMemory Modules: supercell (i,j)64 MB memory moduleconsisting ofeight 8Mx8 DRAMsaddr (row = i, col = j)MemorycontrollerDRAM 7DRAM 0031 78151623243263 39404748555664-bit doubleword at main memory address Abits0-7bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword031 78151623243263 39404748555664-bit doubleword at main memory address A– 8 –CS 105Typical Bus Structure Connecting CPU and MemoryTypical Bus Structure Connecting CPU and MemoryA A busbus is a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signalsaddress, data, and control signalsBuses are typically shared by multiple devicesBuses are typically shared by multiple devicesmainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem bus memory bus– 9 –CS 105Memory Read Transaction (1)Memory Read Transaction (1)CPU places address A on memory busCPU places address A on memory bus ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax– 10 –CS 105Memory Read Transaction (2)Memory Read Transaction (2)Main memory reads A from memory bus, retrieves word Main memory reads A from memory bus, retrieves word x, and places it on busx, and places it on busALUregister filebus interfacex0Axmain memory%eaxI/O bridgeLoad operation: movl A, %eax– 11 –CS 105Memory Read Transaction (3)Memory Read Transaction (3)CPU reads word x from bus and copies it into register CPU reads word x from bus and copies it into register %eax%eaxxALUregister filebus interfacexmain memory0A%eaxI/O bridgeLoad operation: movl A, %eax– 12 –CS 105Memory Write Transaction (1)Memory Write Transaction (1) CPU places address A on bus; main memory reads it CPU places address A on bus; main memory reads it and waits for corresponding data word to arriveand waits for corresponding data word to arriveyALUregister filebus interfaceAmain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 13 –CS 105Memory Write Transaction (2)Memory Write Transaction (2) CPU places data word y on busCPU places data word y on busyALUregister filebus interfaceymain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 14 –CS 105Memory Write Transaction (3)Memory Write Transaction (3) Main memory reads data word y from bus and stores it Main memory reads data word y from bus and stores it at address Aat address AyALUregister filebus interfaceymain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 15 –CS 105Disk GeometryDisk GeometryDisks consist of Disks consist of plattersplatters, each with two , each with two surfacessurfacesEach surface consists of concentric rings called Each surface consists of concentric rings called trackstracksEach track consists of Each track consists of sectorssectors separated by separated by gapsgapsspindlesurfacetrackstrack ksectorsgaps– 16 –CS 105Disk Geometry(Muliple-Platter View)Disk Geometry(Muliple-Platter View) Aligned tracks form a Aligned tracks form a cylindercylindersurface 0surface 1surface 2surface
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