CS 105 Tour of the Black Holes of Computing The Memory Hierarchy Topics Storage technologies and trends Locality of reference Caching in the memory hierarchy Random Access Memory RAM Key features RAM is packaged as a chip Basic storage unit is a cell one bit per cell Multiple RAM chips form a memory Static RAM SRAM Each cell stores bit with a six transistor circuit Retains value indefinitely as long as it is kept powered Relatively insensitive to disturbances such as electrical noise Faster and more expensive than DRAM Dynamic RAM DRAM 2 Each cell stores bit with a capacitor and transistor Value must be refreshed every 10 100 ms Sensitive to disturbances Slower and cheaper than SRAM CS 105 Non Volatile RAM NVRAM Key Feature Keeps data when power lost Several types Most important is NAND flash Ongoing R D NAND flash Reading similar to DRAM though somewhat slower Writing packed with restrictions Can t change existing data Must erase in large blocks e g 64K Block dies after about 100K erases Writing slower than reading mostly due to erase cost Chips often packaged with Flash Translation Layer FTL Spreads out writes wear leveling Makes chip appear like disk drive 3 CS 105 Conventional DRAM Organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 0 addr to CPU 2 3 0 2 bits rows memory controller 1 cols 1 supercell 2 1 2 8 bits 3 data 4 internal row buffer CS 105 Reading DRAM Supercell 2 1 Step 1 a Row address strobe RAS selects row 2 Step 1 b Row 2 copied from DRAM array to row buffer 16 x 8 DRAM chip 0 RAS 2 2 2 3 0 addr rows memory controller 1 cols 1 2 8 3 data 5 internal row buffer CS 105 Reading DRAM Supercell 2 1 Step 2 a Column access strobe CAS selects column 1 Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to CPU 16 x 8 DRAM chip 0 CAS 1 2 rows memory controller supercell 2 1 2 3 0 addr To CPU 1 cols 1 2 8 3 data 6 supercell 2 1 internal row buffer CS 105 Memory Modules addr row i col j supercell i j DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs DRAM 7 bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 bits 0 7 0 64 bit doubleword at main memory address A Memory controller 64 bit doubleword 7 CS 105 Typical Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address data and control signals Buses are typically shared by multiple devices CPU chip register file ALU system bus bus interface 8 I O bridge memory bus main memory CS 105 Memory Read Transaction 1 CPU places address A on memory bus register file eax Load operation movl A eax ALU I O bridge bus interface 9 A main memory 0 x A CS 105 Memory Read Transaction 2 Main memory reads A from memory bus retrieves word x and places it on bus register file eax Load operation movl A eax ALU I O bridge bus interface 10 x main memory 0 x A CS 105 Memory Read Transaction 3 CPU reads word x from bus and copies it into register eax register file eax x Load operation movl A eax ALU I O bridge bus interface 11 main memory 0 x A CS 105 Memory Write Transaction 1 CPU places address A on bus main memory reads it and waits for corresponding data word to arrive register file eax y Store operation movl eax A ALU I O bridge bus interface 12 A main memory 0 A CS 105 Memory Write Transaction 2 CPU places data word y on bus register file eax y Store operation movl eax A ALU I O bridge bus interface 13 y main memory 0 A CS 105 Memory Write Transaction 3 Main memory reads data word y from bus and stores it at address A register file eax y Store operation movl eax A ALU I O bridge bus interface 14 main memory 0 y A CS 105 Disk Geometry Disks consist of platters each with two surfaces Each surface consists of concentric rings called tracks Each track consists of sectors separated by gaps tracks surface track k gaps spindle sectors 15 CS 105 Disk Geometry Muliple Platter View Aligned tracks form a cylinder cylinder k surface 0 platter 0 surface 1 surface 2 platter 1 surface 3 surface 4 platter 2 surface 5 spindle 16 CS 105 Disk Operation Single Platter View The disk surface spins at a fixed rotational rate Read write head is attached to end of the arm and flies over disk surface on thin cushion of air spindle By moving radially arm can position read write head over any track 17 CS 105 Disk Operation Multi Platter View read write heads move in unison from cylinder to cylinder arm spindle 18 CS 105 Disk Access Time Average time to access some target sector approximated by Taccess Tavg seek Tavg rotation Tavg transfer Seek time Tavg seek Time to position heads over cylinder containing target sector Typical Tavg seek 9 ms Rotational latency Tavg rotation Time waiting for first bit of target sector to pass under r w head Tavg rotation 1 2 x 1 RPMs x 60 sec 1 min Transfer time Tavg transfer 19 Time to read the bits in the target sector Tavg transfer 1 RPM x 1 avg sectors track x 60 secs 1 min CS 105 Disk Access Time Example Given Rotational rate 7 200 RPM Average seek time 9 ms Avg sectors track 400 Derived Tavg rotation 1 2 x 60 secs 7200 RPM x 1000 ms sec 4 ms Tavg transfer 60 7200 RPM x 1 400 secs track x 1000 ms sec 0 02 ms Taccess 9 ms 4 ms 0 02 ms Important points 20 Access time dominated by seek time and rotational latency First bit in a sector is the most expensive the rest are free SRAM access time is about 4 ns doubleword DRAM about 60 ns Disk is about 40 000 times slower than SRAM and 2 500 times slower then DRAM CS 105 Logical Disk Blocks Modern disks present a simpler abstract view of the complex sector geometry The set of available sectors is modeled as a sequence of bsized logical blocks 0 1 2 Mapping between logical blocks and actual physical sectors Maintained by hardware firmware device called disk controller Converts requests for logical blocks into surface track sector triples Allows controller to set aside spare cylinders for each zone 21 Accounts for the difference in formatted capacity and maximum capacity CS 105 I O Bus CPU chip register file ALU system bus memory bus main memory I O bridge bus interface I O bus USB controller …
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