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Harvey Mudd CS 105 - The Memory Hierarchy

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The Memory HierarchyRandom-Access Memory (RAM)Conventional DRAM OrganizationReading DRAM Supercell (2,1)Slide 6Memory ModulesTypical Bus Structure Connecting CPU and MemoryMemory Read Transaction (1)Memory Read Transaction (2)Memory Read Transaction (3)Memory Write Transaction (1)Memory Write Transaction (2)Memory Write Transaction (3)Disk GeometryDisk Geometry (Muliple-Platter View)Disk Operation (Single-Platter View)Disk Operation (Multi-Platter View)Disk Access TimeDisk Access Time ExampleLogical Disk BlocksI/O BusReading a Disk Sector (1)Reading a Disk Sector (2)Reading a Disk Sector (3)Storage TrendsCPU Clock RatesThe CPU-Memory GapLocalityLocality ExampleSlide 36Slide 37Memory HierarchiesAn Example Memory HierarchyCachesCaching in a Memory HierarchyGeneral Caching ConceptsGeneral Caching ConceptsExamples of Caching in the HierarchyThe Memory HierarchyThe Memory HierarchyTopicsTopicsStorage technologies and trendsLocality of referenceCaching in the memory hierarchyCS 105Tour of the Black Holes of Computing– 2 –CS 105Random-Access Memory (RAM)Random-Access Memory (RAM)Key featuresKey featuresRAM is packaged as a chip.Basic storage unit is a cell (one bit per cell).Multiple RAM chips form a memory.Static RAM (Static RAM (SRAMSRAM))Each cell stores bit with a six-transistor circuit.Retains value indefinitely, as long as it is kept powered.Relatively insensitive to disturbances such as electrical noise.Faster and more expensive than DRAM.Dynamic RAM (Dynamic RAM (DRAMDRAM))Each cell stores bit with a capacitor and transistor.Value must be refreshed every 10-100 ms.Sensitive to disturbances.Slower and cheaper than SRAM.– 4 –CS 105Conventional DRAM OrganizationConventional DRAM Organizationd x w DRAM:d x w DRAM:dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)– 5 –CS 105Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 1(a): Row address strobe (Step 1(a): Row address strobe (RASRAS) selects row 2.) selects row 2.colsrowsRAS = 201 2 3012internal row buffer16 x 8 DRAM chip3addrdata2/8/memorycontrollerStep 1(b): Row 2 copied from DRAM array to row buffer.Step 1(b): Row 2 copied from DRAM array to row buffer.– 6 –CS 105Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 2(a): Column access strobe (Step 2(a): Column access strobe (CASCAS) selects column 1.) selects column 1.colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerStep 2(b): Supercell (2,1) copied from buffer to data lines, Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.and eventually back to the CPU.supercell (2,1)supercell (2,1)To CPU– 7 –CS 105Memory ModulesMemory Modules: supercell (i,j)64 MB memory moduleconsisting ofeight 8Mx8 DRAMsaddr (row = i, col = j)MemorycontrollerDRAM 7DRAM 0031 78151623243263 39404748555664-bit doubleword at main memory address Abits0-7bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword031 78151623243263 39404748555664-bit doubleword at main memory address A– 10 –CS 105Typical Bus Structure Connecting CPU and MemoryTypical Bus Structure Connecting CPU and MemoryA A busbus is a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signals.address, data, and control signals.Buses are typically shared by multiple devices.Buses are typically shared by multiple devices.mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem bus memory bus– 12 –CS 105Memory Read Transaction (1)Memory Read Transaction (1)CPU places address A on the memory bus.CPU places address A on the memory bus. ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax– 13 –CS 105Memory Read Transaction (2)Memory Read Transaction (2)Main memory reads A from the memory bus, retrieves Main memory reads A from the memory bus, retrieves word x, and places it on the bus.word x, and places it on the bus.ALUregister filebus interfacex0Axmain memory%eaxI/O bridgeLoad operation: movl A, %eax– 14 –CS 105Memory Read Transaction (3)Memory Read Transaction (3)CPU reads word x from the bus and copies it into CPU reads word x from the bus and copies it into register %eax.register %eax.xALUregister filebus interfacexmain memory0A%eaxI/O bridgeLoad operation: movl A, %eax– 15 –CS 105Memory Write Transaction (1)Memory Write Transaction (1) CPU places address A on bus. Main memory reads it CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive.and waits for the corresponding data word to arrive.yALUregister filebus interfaceAmain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 16 –CS 105Memory Write Transaction (2)Memory Write Transaction (2) CPU places data word y on the bus.CPU places data word y on the bus.yALUregister filebus interfaceymain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 17 –CS 105Memory Write Transaction (3)Memory Write Transaction (3) Main memory reads data word y from the bus and Main memory reads data word y from the bus and stores it at address A.stores it at address A.yALUregister filebus interfaceymain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 18 –CS 105Disk GeometryDisk GeometryDisks consist of Disks consist of plattersplatters, each with two , each with two surfacessurfaces..Each surface consists of concentric rings called Each surface consists of concentric rings called trackstracks..Each track consists of Each track consists of sectorssectors separated by separated by gapsgaps..spindlesurfacetrackstrack ksectorsgaps– 19 –CS 105Disk Geometry(Muliple-Platter View)Disk Geometry(Muliple-Platter View) Aligned tracks form a Aligned tracks form a cylindercylinder..surface 0surface 1surface 2surface 3surface 4surface 5cylinder kspindleplatter 0platter 1platter 2– 22 –CS 105Disk Operation (Single-Platter View)Disk Operation (Single-Platter View) The disk surface spins at a fixedrotational ratespindleBy moving radially, the arm can position the read/write head over any track.The read/write headis attached to the endof the arm and flies overthe disk surface ona thin cushion of air.spindle– 23 –CS 105Disk Operation (Multi-Platter View)Disk Operation (Multi-Platter View) armread/write heads move in unisonfrom


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Harvey Mudd CS 105 - The Memory Hierarchy

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