CS 105 Tour of the Black Holes of Computing Machine Dependent Optimization Machine Dependent Optimization Need to understand the architecture Not portable Not often needed but critically important when it is Also helps in understanding modern machines 2 CS 105 Modern CPU Design Instruction Control Fetch Control Retirement Unit Register File Address Instrs Instruction Decode Instruction Cache Operations Register Updates Prediction OK Integer Branch General Integer FP Add Operation Results FP Mult Div Load Addr Store Functional Units Addr Data Data Data Cache Execution 3 CS 105 CPU Capabilities of Pentium III Multiple Instructions Can Execute in Parallel 1 load 1 store 2 integer one may be branch 1 FP Addition 1 FP Multiplication or Division Some Instructions Take 1 Cycle But Can Be Pipelined Instruction 4 Latency Cycles Issue Load Store 3 1 Integer Multiply 4 1 Integer Divide 36 Double Single FP Multiply 5 Double Single FP Add 1 Double Single FP Divide 36 3 38 2 38 CS 105 What Is a Pipeline Add Result Bucket 5 CS 105 Instruction Control Instruction Control Retirement Unit Register File Fetch Control Instruction Decode Address Instrs Instruction Cache Operations Grabs instruction bytes from memory Based on current PC targets for predicted branches Hardware dynamically guesses whether branches taken not taken and possibly branch target Translates instructions into operations unique x86 feature Primitive steps required to perform instruction Typical instruction requires 1 3 operations Converts register references into tags 6 Abstract identifier linking destination of one operation with sources of later operations CS 105 Translation Example Version of Combine4 Integer data multiply operation Translation of First Iteration L24 imull eax edx 4 ecx incl edx cmpl esi edx jl L24 Loop t data i i i length if goto Loop L24 imull eax edx 4 ecx incl edx cmpl esi edx jl L24 7 load eax edx 0 4 imull t 1 ecx 0 incl edx 0 cmpl esi edx 1 jl taken cc 1 t 1 ecx 1 edx 1 cc 1 CS 105 Translation Example 1 imull eax edx 4 ecx Split into two operations Operands load eax edx 0 4 t 1 imull t 1 ecx 0 ecx 1 load reads from memory to generate temporary result t 1 Multiply operation just operates on registers Register eax does not change in loop Values will be retrieved from register file during decoding Register ecx changes on every iteration Uniquely identify different ver sions as ecx 0 ecx 1 ecx 2 Register renaming Values passed directly from producer to consumers 8 CS 105 Translation Example 2 incl edx 9 incl edx 0 edx 1 Register edx changes on each iteration Rename as edx 0 edx 1 edx 2 CS 105 Translation Example 3 cmpl esi edx cmpl esi edx 1 Condition codes are treated similarly Assign tag to define connection between producer and consumer 10 cc 1 CS 105 Translation Example 4 jl L24 jl taken cc 1 Instruction control unit determines destination of jump Predicts whether will be taken and target Starts fetching instruction at predicted destination Execution unit simply checks whether or not prediction was OK If not it signals instruction control Instruction control then invalidates any operations generated from misfetched instructions Begins fetching and decoding instructions at correct target 11 CS 105 Visualizing Operations edx 0 incl load load eax edx 4 imull t 1 ecx 0 incl edx 0 cmpl esi edx 1 jl taken cc 1 edx 1 cmpl cc 1 ecx 0 jl t 1 ecx 1 edx 1 cc 1 t 1 Time Operations imull Vertical position denotes time at which executed Cannot begin operation until operands available ecx 1 Height denotes latency Operands 12 Arcs shown only for operands that are passed within execution unit CS 105 Visualizing Operations cont edx 0 load incl load cmpl 1 ecx i edx 1 load eax edx 4 addl t 1 ecx 0 incl edx 0 cmpl esi edx 1 jl taken cc 1 t 1 ecx 1 edx 1 cc 1 cc 1 ecx 0 Time jl t 1 addl ecx 1 Operations 13 Same as before except that add has latency of 1 CS 105 3 Iterations of Combining Product Unlimited Resource Analysis edx 0 incl 1 load 2 cmpl cc 1 jl 3 incl load cc 2 i 0 4 edx 2 cmpl t 1 ecx 0 5 edx 1 jl incl load Assume operation can start as soon as operands available Operations for multiple iterations overlap in time edx 3 cmpl t 2 cc 3 jl imull t 3 6 7 ecx 1 Iteration 1 8 9 10 11 12 13 Performance imull Cycle i 1 Limiting factor becomes latency of integer multiplier Gives CPE of 4 0 ecx 2 Iteration 2 imull 14 i 2 15 ecx 3 14 Iteration 3 CS 105 4 Iterations of Combining Sum edx 0 incl 1 load 2 3 load i 0 ecx 1 Iteration 1 5 6 incl t 1 addl 4 cmpl 1 ecx i cc 1 jl ecx 0 edx 1 Cycle edx 2 cmpl 1 ecx i cc 2 jl incl load t 2 addl i 1 ecx 2 Iteration 2 cmpl 1 ecx i cc 3 jl incl load t 3 addl i 2 ecx 3 Iteration 3 7 edx 3 Unlimited Resource Analysis edx 4 4 integer ops cmpl 1 ecx i cc 4 jl t 4 addl i 3 ecx 4 Iteration 4 Performance 15 Can begin a new iteration on each clock cycle Should give CPE of 1 0 Would require executing 4 integer operations in parallel CS 105 Combining Sum Resource Constraints edx 3 6 load 7 8 ecx 3 incl cmpl 1 ecx i t 4 jl ecx 4 11 Iteration 4 12 addl ecx 5 cmpl 1 ecx i cc 5 load edx 6 i 4 t 6 addl cmpl load cc 6 cc 6 jl i 5 incl t 7 addl Iteration 6 15 Only have two integer functional units 16 Cycle 17 Some operations delayed even though operands available 18 Set priority based on program order Performance Sustain 16 incl jl ecx 6 14 t 5 Iteration 5 13 edx 5 load i 3 10 incl cc 4 addl 9 edx 4 CPE of 2 0 edx 7 cmpl cc 7 jl load i 6 ecx 7 Iteration 7 t 8 addl incl edx 8 cmpl 1 ecx i cc 8 jl i 7 ecx 8 Iteration 8 CS 105 Loop Unrolling void combine5 vec ptr v int dest int length vec length v int limit length 2 int data get vec start v int sum 0 int i Combine 3 elements at a time for i 0 i limit i 3 sum data i data i 2 data i 1 Finish any remaining elements for i length i sum data i dest sum 17 Optimization Combine multiple iterations into single loop body Amortizes loop overhead across multiple iterations Finish extras at end Measured CPE 1 33 CS 105 Visualizing Unrolled Loop edx 0 Loads can pipeline since don t have dependencies Only one set of loop control operations addl load ecx 0c cmpl 1 ecx i load ecx 1a t …
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