P6/Linux Memory SystemIntel P6P6 Memory SystemReview of AbbreviationsOverview of P6 Address TranslationP6 2-Level Page Table StructureP6 Page Table Entry (PTE)P6 Page Directory Entry (PDE)How P6 Page Tables Map Virtual Addresses to Physical OnesRepresentation of Virtual Address SpaceP6 TLB TranslationP6 TLBTranslating with the P6 TLBP6 page table translationTranslating with the P6 Page Tables (case 1/1)Translating with the P6 Page Tables (case 1/0)Translating with the P6 Page Tables (case 1/0, cont.)Translating with the P6 Page Tables (case 0/1)Translating with the P6 Page Tables (case 0/0)Translating with the P6 Page Tables (case 0/0, cont.)P6 L1 Cache AccessL1 Cache AccessSpeeding Up L1 AccessLinux Organizes VM as Collection of “Areas”Linux Page Fault HandlingMemory MappingCopy on WriteUser-Level Memory Mappingmmap() Example: String Searchmmap() Example: Fast File CopyMemory System SummaryP6/Linux Memory SystemP6/Linux Memory SystemTopicsTopicsP6 address translationLinux memory managementLinux page fault handlingMemory mappingCS 105“Tour of the Black Holes of Computing!”– 2 –CS 105Intel P6Intel P6Internal designation for successor to PentiumInternal designation for successor to PentiumPentium had internal designation P5Fundamentally different from PentiumFundamentally different from PentiumOut-of-order, superscalar operationDesigned to handle server applicationsRequires high-performance memory systemResulting processorsResulting processorsPentiumPro (1996)Pentium II (1997)Incorporated MMX instructions»Special instructions for parallel processingL2 cache on same chipPentium III (1999)Incorporated Streaming SIMD Extensions (SSE)»More instructions for parallel processing– 3 –CS 105P6 Memory SystemP6 Memory Systembus interface unitDRAMexternal system bus (e.g. PCI)instruction fetch unitL1i-cacheL2cachecache busL1d-cacheinstTLBdataTLBprocessor package 32-bit address space32-bit address space 4 KB page size4 KB page size L1, L2, and TLBsL1, L2, and TLBs 4-way set associative inst TLBinst TLB 32 entries 8 sets data TLBdata TLB 64 entries 16 sets L1 i-cache and d-cacheL1 i-cache and d-cache 16 KB 32 B line size 128 sets L2 cacheL2 cache unified 128 KB - 2 MB– 4 –CS 105Review of AbbreviationsReview of AbbreviationsSymbols:Symbols:Components of the virtual address (VA)VPO: virtual page offset VPN: virtual page number TLBI: TLB indexTLBT: TLB tagComponents of the physical address (PA)PPO: physical page offset (same as VPO)PPN: physical page numberCO: byte offset within cache lineCI: cache indexCT: cache tag– 5 –CS 105Overview of P6 Address TranslationOverview of P6 Address TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 and DRAML1 (128 sets, 4 lines/set)L1hitL1miss– 6 –CS 105P6 2-Level Page Table StructureP6 2-Level Page Table StructurePage directory Page directory 1024 4-byte page directory entries (PDEs) that point to page tablesOne page directory per process.Page directory must be in memory when its process is runningAlways pointed to by PDBRPage tables:Page tables:1024 4-byte page table entries (PTEs) that point to pages.Page tables can be paged in and out.page directory...Up to 1024 page tables1024PTEs1024PTEs1024PTEs...1024PDEs– 7 –CS 105P6 Page Table Entry (PTE)P6 Page Table Entry (PTE)Page physical base address Avail G 0 D A CD WT U/S R/W P=1Page base address: 20 most significant bits of physical page address (forces pages to be 4 KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)D: dirty (set by MMU on writes)A: accessed (set by MMU on reads and writes, cleared by software) CD: cache disabled (0) or enabled (1) for this pageWT: write-through or write-back cache policy for this pageU/S: user/supervisorR/W: read/writeP: page is present in physical memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page location in secondary storage) P=031 01– 8 –CS 105P6 Page Directory Entry (PDE)P6 Page Directory Entry (PDE)Page table physical base addr Avail G PS 0 A CD WT U/S R/W P=1Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB-aligned)Avail: These bits available for system programmersG: global page (don’t evict from TLB on task switch)PS: page size 4K (0) or 4M (1)A: accessed (set by MMU on reads and writes, cleared by software) CD: cache disabled (1) or enabled (0) for this page tableWT: write-through or write-back cache policy for this page tableU/S: user or supervisor mode accessR/W: read-only or read-write accessP: page table is present in memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page table location in secondary storage) P=031 01– 9 –CS 105How P6 Page Tables Map VirtualAddresses to Physical OnesHow P6 Page Tables Map VirtualAddresses to Physical OnesPDEPDBRphysical addressof page table base(if P=1)physical addressof page base(if P=1)physical addressof page directoryword offset into page directoryword offset into page tablepage directory page tableVPN110VPO10 12VPN2Virtual addressPTEPPN PPO2012Physical addressword offset into physical and virtualpage– 10 –CS 105Representation of Virtual Address SpaceRepresentation of Virtual Address SpaceSimplified ExampleSimplified Example16 page virtual address spaceFlagsFlagsP: Is entry in physical memory?M: Has this part of VA space been mapped?Page DirectoryPT 3P=1, M=1P=1, M=1P=0, M=0P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=1, M=1P=0, M=0P=1, M=1P=0, M=1••••P=0, M=1P=0, M=1P=0, M=0P=0, M=0••••PT 2PT 0Page 0Page 1Page 2Page 3Page 4Page 5Page 6Page 7Page 8Page 9Page 10Page 11Page 12Page 13Page 14Page 15Mem AddrDisk AddrIn MemOn DiskUnmapped– 11 –CS 105P6 TLB TranslationP6 TLB TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 and DRAML1 (128 sets, 4 lines/set)L1hitL1miss– 12 –CS 105P6 TLBP6 TLBTLB entry (not all documented, so this is speculative):TLB entry (not all documented, so this is speculative):V: indicates a valid (1) or invalid (0) TLB entryPD: is
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