CS 105 Tour of the Black Holes of Computing Cache Memories Topics cache ppt Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance New Topic Cache Buffer between processor and memory Often several levels of caches Small but fast Old values will be removed from cache to make space for new values Capitalizes on spatial locality and temporal locality Spatial locality If a value is used nearby values are likely to be used Temporal locality If a value is used it is likely to be used again soon Parameters vary by system unknown to programmer Cache friendly code 2 CS105 Cache Memories Cache memories are small fast SRAM based memories managed automatically in hardware Hold frequently accessed blocks of main memory CPU looks first for data in L1 then in L2 then in main memory Typical bus structure CPU chip register file cache bus L2 cache 3 L1 cache bus interface ALU system bus memory bus I O bridge main memory CS105 Inserting an L1 Cache Between the CPU and Main Memory The tiny very fast CPU register file has room for four 4 byte words The transfer unit between the CPU register file and the cache is a 4 byte block line 0 The small fast L1 cache has room for two 4 word blocks line 1 The transfer unit between the cache and main memory is a 4 word block 16 bytes block 10 abcd block 21 pqrs block 30 wxyz 4 The big slow main memory has room for many 4 word blocks CS105 General Org of a Cache Memory Cache is an array of sets Each set contains one or more lines 1 valid bit t tag bits per line per line valid set 0 Each line holds a block of data S 2s sets set 1 tag B 2b bytes per cache block 0 1 B 1 valid tag 0 1 B 1 valid tag 0 1 B 1 1 B 1 1 B 1 1 B 1 E lines per set valid tag 0 valid set S 1 5 tag 0 valid tag 0 Cache size C B x E x S data bytes CS105 Addressing Caches Address A t bits set 0 set 1 v tag v tag v tag v tag 0 0 1 B 1 1 B 1 0 0 1 B 1 1 B 1 1 B 1 1 B 1 set S 1 6 v tag v tag 0 0 s bits b bits m 1 0 tag set index block offset The word at address A is in the cache if the tag bits in one of the valid lines in set set index match tag The word contents begin at offset block offset bytes from the beginning of the block CS105 Direct Mapped Cache Simplest kind of cache Characterized by exactly one line per set set 0 valid tag cache block set 1 valid tag cache block E 1 lines per set set S 1 7 valid tag cache block CS105 Accessing Direct Mapped Caches Set selection Use the set index bits to determine the set of interest selected set set 0 valid tag cache block set 1 valid tag cache block t bits m 1 tag 8 s bits b bits 00 001 set index block offset0 set S 1 valid tag cache block CS105 Accessing Direct Mapped Caches Line matching and word selection Line matching Find a valid line in the selected set with a matching tag Word selection Then extract the word 1 1 The valid bit must be set 0 selected set i 1 0110 1 2 3 4 w0 5 w1 w2 2 The tag bits in the cache line must match the tag bits in the address m 1 9 t bits 0110 tag 6 s bits b bits i 100 set index block offset0 7 w3 3 If 1 and 2 then cache hit and block offset selects starting byte CS105 Direct Mapped Cache Simulation t 1 s 2 x xx M 16 byte addresses B 2 bytes block S 4 sets E 1 entry set b 1 x v 11 Address trace reads 0 00002 1 00012 13 11012 8 10002 0 00002 0 00002 miss tag data 0 0 m 1 m 0 M 0 1 1 3 v 11 4 10 13 11012 miss v tag data 1 8 10002 miss tag data 1 1 m 9 m 8 M 8 9 1 M 12 13 1 1 0 0 1 1 1 m 13 m 12 1 M 12 13 v 0 00002 miss tag data 11 5 11 m 1 m 0 M 0 1 0 0 m 1 m 0 M 0 1 1 1 m 13 m 12 M 12 13 CS105 Why Use Middle Bits as Index High Order Bit Indexing 4 line Cache 00 01 10 11 High Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle Order Bit Indexing 11 Consecutive memory lines map to different cache lines Can hold C byte region of address space in cache at one time 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Middle Order Bit Indexing CS105 Set Associative Caches Characterized by more than one line per set set 0 set 1 valid tag cache block valid tag cache block valid tag cache block valid tag cache block E 2 lines per set set S 1 12 valid tag cache block valid tag cache block CS105 Accessing Set Associative Caches Set selection identical to direct mapped cache set 0 Selected set set 1 valid tag cache block valid tag cache block valid tag cache block valid tag cache block t bits m 1 tag 13 set S 1 s bits b bits 00 001 set index block offset0 valid tag cache block valid tag cache block CS105 Accessing Set Associative Caches Line matching and word selection must compare the tag in each valid line in the selected set 1 1 The valid bit must be set 0 selected set i 1 1001 1 0110 2 The tag bits in one of the cache lines must match the tag bits in the address 2 3 4 w0 t bits 0110 tag 5 6 w1 w2 7 w3 3 If 1 and 2 then cache hit and block offset selects starting byte m 1 14 1 s bits b bits i 100 set index block offset0 CS105 Multi Level Caches Options separate data and instruction caches or a unified cache Processor Regs L1 d cache L1 i cache size speed Mbyte line size 15 200 B 3 ns 8 64 KB 3 ns 8B 32 B larger slower cheaper Unified Unified L2 L2 Cache Cache 1 4MB SRAM 6 ns 100 MB 32 B Memory Memory 128 MB DRAM 60 ns 1 50 MB 8 KB disk disk 30 GB 8 ms 0 05 MB CS105 Intel Pentium Cache Hierarchy Regs L1 Data 1 cycle latency …
View Full Document
Unlocking...