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UW-Madison ECE 353 - ECE 353 Lecture Notes

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ECE 353 Introduction to Microprocessor SystemsTopicsMOV InstructionShifter OperandsConditional Execution and FlagsMOV Special CasesSpecialized MovesData Processing InstructionsData Processing - LogicalData Processing - ArithmeticMultiply-AccumulateMemory Addressing ModelsMemory Addressing ModesMemory Addressing Modes (cont)Slide 15Slide 16Slide 17ARM7TDMI Memory AllocationARM7 Memory Addressing ModesARM7 Load/Store InstructionsARM7 Load/Store AddressingARM7 Load/Store Addressing (cont)ARM7 Load/Store Instructions (cont)ARM7 Load/Store MultipleARM7 Memory Pseudo-InstructionsIn-Class ExerciseWrapping UpHungarian NotationARM7 Condition CodesMOV Instruction ReferenceLDRB Instruction ReferenceSWPB Instruction ReferenceTeam ConcepTestOne Minute PaperECE 353Introduction to Microprocessor SystemsMichael SchulteWeek 4Data movement instructionsShifter operandsSpecial cases with PC as destinationARM7TDMI ISA UsageConditional execution and flags updatesSpecial cases of encodingData Processing InstructionsMemory Addressing Models and ModesMemory AllocationAllocation directives, alignmentARM7TDMI Load/Store InstructionsAddressing modesTopics“Complexity is our friend.”MOV InstructionSyntaxMOV{<cond>}{S} <Rd>, <shifter_operand>RTLif (cond is true) Rd  shifter_operandif((S==1) AND (Rd==R15))CPSR  SPSRFlags (if S is appended and Rd is not R15)N, Z, C (C is based on shifter operand)31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0cond 0 0 I 1 1 0 1 S SBZ Rd shifter operandShifter OperandsImmediate (I=1)8-bit value, 4-bit rotate codeSignified by #<number>RegisterNo shiftShifted RegisterLSL, LSR, ASR, RORShift count from immediate or registerRotate Right with ExtendRotates register right 1 bit through CARRY flagConditional Execution and FlagsIf a condition is used, the instruction will only be executed if the condition is true.Flags are only updated if S is usedSome instructions (B, BL, CMP, CMN, TST, TEQ, etc.) don’t use SUsing flags and conditionsMOVS R1, R1MOV R0, #1MOVEQ R0, #0MOVMI R0, #-1MOV Special CasesIf R15 is the destination of a MOV instruction and S is appendedMOVS R15, R?In addition to the move into the PC, the CPSR is loaded from the current exception mode’s SPSR. Flags are not affected.This behavior is intended to only be used to return from exception modes.Do not do this in user or system mode – there is no SPSR and the results are unpredictable!Specialized MovesMVN – move negatedShifter operand is complementedNote that this is a 1’s-complement (NOT)MRS – move CPSR/SPSR to GP registerMSR – move GP register to CPSR/SPSRSWP – swapSWPB – swap byteSwap instructions exchange values between memory and registers in an atomic operationData Processing InstructionsThe data processing instructions all use a very similar structure for operands, including a shifter operandMnemonic{cond}{S} Rd, Rn, <shifter_operand>In general, Rd  Rn operation shifter_operandThe non-destructive instructions will not use a destination register (Rd).Some instructions reverse the operand orderSince shifts can be part of any MOV or data processing instruction, there are no dedicated shift instructions.Data Processing - LogicalAND – bit-wise ANDBIC – bit clear (bit-wise AND with complement of shifter operand)EOR – bit-wise exclusive-ORORR – bit-wise inclusive-ORTEQ – test equivalence (non-destructive XOR)TST – test (non-destructive AND)Data Processing - ArithmeticADC – add with carryADD – addCMN – compare negativeCMP – compareRSB – reverse subtractRSC – reverse subtract with carrySBC – subtract with carrySUB - subtractMultiply-Accumulate32x32 multiplies - 32-bit resultMLA – multiply-accumulateMUL – multiply32x32 multiplies - 64-bit result SMLAL – signed long multiply-accumulateSMULL – signed long multiplyUMLAL – unsigned long multiply-accumulateUMULL – unsigned long multiplyMemory Addressing ModelsLinear Memory AddressingInstructions can specify the complete addressSegmented Memory AddressingInstructions do not contain the full address, just part of it (the offset)The remainder of the address is furnished by a page register or a segment registerThere may be multiple segment registersThe full physical address is formed by combining the segment/page register and the offset from the instructionAdvantages / disadvantagesMemory Addressing ModesDirect AddressingThe operand address is encoded into the instruction. In variable length instructions, the full physical address can usually be encoded.In fixed length instructions, usually only the least significant part of the address can be encodedThe remainder of the address can be set to 0 (base page addressing)The remainder of the address can be obtained from a page register or segment register.Memory Addressing Modes (cont)Register Indirect AddressingThe instruction specifies a register that contains the memory address to accessMay also support updating the register as part of the instruction (auto-increment, auto-decrement, etc.)Memory Indirect AddressingA memory location (encoded in the instruction) contains the address to transfer to/fromMemory Addressing Modes (cont)Indexed AddressingThe physical address is calculated from a constant starting address (encoded in the instruction) and the contents of a registerTypically used for accessing data in arraysBase address = array starting addressRegister holds (element index × element size)If byte array, element size = 1If halfword array, element size = 2If word array, element size = 4The processor may do the index * element size calculation automaticallyBased AddressingThe physical address is calculated from a base address contained in a register, plus a constant offset encoded in the instructionTypically used for accessing information in data structures.Register holds starting address of structure.Offset is distance from the start of the structure to the desired structure element.Code can then access any instance of the structure just by changing register contents to point to it.Memory Addressing Modes (cont)PC-Relative AddressingThe address is computed by adding an offset value encoded in the instruction to the current value of the program counter.In many microprocessors, the PC is not part of the programmer’s


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