ECE 353 Introduction to Microprocessor SystemsTopicsMOV InstructionShifter OperandsConditional Execution and FlagsMOV Special CasesSpecialized MovesData Processing InstructionsData Processing - LogicalData Processing - ArithmeticMultiply-AccumulateMemory Addressing ModelsMemory Addressing ModesMemory Addressing Modes (cont)Slide 15Slide 16Slide 17ARM7TDMI Memory AllocationARM7 Memory Addressing ModesARM7 Load/Store InstructionsARM7 Load/Store AddressingARM7 Load/Store Addressing (cont)ARM7 Load/Store Instructions (cont)ARM7 Load/Store MultipleARM7 Memory Pseudo-InstructionsIn-Class ExerciseWrapping UpHungarian NotationARM7 Condition CodesMOV Instruction ReferenceLDRB Instruction ReferenceSWPB Instruction ReferenceTeam ConcepTestOne Minute PaperECE 353Introduction to Microprocessor SystemsMichael SchulteWeek 4Data movement instructionsShifter operandsSpecial cases with PC as destinationARM7TDMI ISA UsageConditional execution and flags updatesSpecial cases of encodingData Processing InstructionsMemory Addressing Models and ModesMemory AllocationAllocation directives, alignmentARM7TDMI Load/Store InstructionsAddressing modesTopics“Complexity is our friend.”MOV InstructionSyntaxMOV{<cond>}{S} <Rd>, <shifter_operand>RTLif (cond is true) Rd shifter_operandif((S==1) AND (Rd==R15))CPSR SPSRFlags (if S is appended and Rd is not R15)N, Z, C (C is based on shifter operand)31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0cond 0 0 I 1 1 0 1 S SBZ Rd shifter operandShifter OperandsImmediate (I=1)8-bit value, 4-bit rotate codeSignified by #<number>RegisterNo shiftShifted RegisterLSL, LSR, ASR, RORShift count from immediate or registerRotate Right with ExtendRotates register right 1 bit through CARRY flagConditional Execution and FlagsIf a condition is used, the instruction will only be executed if the condition is true.Flags are only updated if S is usedSome instructions (B, BL, CMP, CMN, TST, TEQ, etc.) don’t use SUsing flags and conditionsMOVS R1, R1MOV R0, #1MOVEQ R0, #0MOVMI R0, #-1MOV Special CasesIf R15 is the destination of a MOV instruction and S is appendedMOVS R15, R?In addition to the move into the PC, the CPSR is loaded from the current exception mode’s SPSR. Flags are not affected.This behavior is intended to only be used to return from exception modes.Do not do this in user or system mode – there is no SPSR and the results are unpredictable!Specialized MovesMVN – move negatedShifter operand is complementedNote that this is a 1’s-complement (NOT)MRS – move CPSR/SPSR to GP registerMSR – move GP register to CPSR/SPSRSWP – swapSWPB – swap byteSwap instructions exchange values between memory and registers in an atomic operationData Processing InstructionsThe data processing instructions all use a very similar structure for operands, including a shifter operandMnemonic{cond}{S} Rd, Rn, <shifter_operand>In general, Rd Rn operation shifter_operandThe non-destructive instructions will not use a destination register (Rd).Some instructions reverse the operand orderSince shifts can be part of any MOV or data processing instruction, there are no dedicated shift instructions.Data Processing - LogicalAND – bit-wise ANDBIC – bit clear (bit-wise AND with complement of shifter operand)EOR – bit-wise exclusive-ORORR – bit-wise inclusive-ORTEQ – test equivalence (non-destructive XOR)TST – test (non-destructive AND)Data Processing - ArithmeticADC – add with carryADD – addCMN – compare negativeCMP – compareRSB – reverse subtractRSC – reverse subtract with carrySBC – subtract with carrySUB - subtractMultiply-Accumulate32x32 multiplies - 32-bit resultMLA – multiply-accumulateMUL – multiply32x32 multiplies - 64-bit result SMLAL – signed long multiply-accumulateSMULL – signed long multiplyUMLAL – unsigned long multiply-accumulateUMULL – unsigned long multiplyMemory Addressing ModelsLinear Memory AddressingInstructions can specify the complete addressSegmented Memory AddressingInstructions do not contain the full address, just part of it (the offset)The remainder of the address is furnished by a page register or a segment registerThere may be multiple segment registersThe full physical address is formed by combining the segment/page register and the offset from the instructionAdvantages / disadvantagesMemory Addressing ModesDirect AddressingThe operand address is encoded into the instruction. In variable length instructions, the full physical address can usually be encoded.In fixed length instructions, usually only the least significant part of the address can be encodedThe remainder of the address can be set to 0 (base page addressing)The remainder of the address can be obtained from a page register or segment register.Memory Addressing Modes (cont)Register Indirect AddressingThe instruction specifies a register that contains the memory address to accessMay also support updating the register as part of the instruction (auto-increment, auto-decrement, etc.)Memory Indirect AddressingA memory location (encoded in the instruction) contains the address to transfer to/fromMemory Addressing Modes (cont)Indexed AddressingThe physical address is calculated from a constant starting address (encoded in the instruction) and the contents of a registerTypically used for accessing data in arraysBase address = array starting addressRegister holds (element index × element size)If byte array, element size = 1If halfword array, element size = 2If word array, element size = 4The processor may do the index * element size calculation automaticallyBased AddressingThe physical address is calculated from a base address contained in a register, plus a constant offset encoded in the instructionTypically used for accessing information in data structures.Register holds starting address of structure.Offset is distance from the start of the structure to the desired structure element.Code can then access any instance of the structure just by changing register contents to point to it.Memory Addressing Modes (cont)PC-Relative AddressingThe address is computed by adding an offset value encoded in the instruction to the current value of the program counter.In many microprocessors, the PC is not part of the programmer’s
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