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UW-Madison ECE 353 - ECE 353 Week 11 Notes

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ECE 353 Introduction to Microprocessor SystemsAdministrative MattersQuiz2 DataTopicsWhy Use Interrupts?Interrupt PrimerInterrupt ConceptsARM7TDMI Interrupt HandlingADuC7026 Hardware InterruptsADuC7026 Interrupt MMRsADuC7026 Programmed InterruptsInterrupt Service RoutinesInterrupt Driven SystemsSoftware Interrupts & ExceptionsInterrupt Prioritization and LatencyInterrupt IssuesIn-Class Assessment QuizSlide 18Wrapping UpInterrupt TerminologyInterrupt Processing SequenceGeneric ImplementationPriority Interrupt ControllerARM7 CPSRARM7 SPSRARM7 Register BankingInterrupt Example - Hardwareaduc7026.sSlide 29SWI Instruction ReferenceADuC7026 Interrupt LatencyADuC7026 Exception PriorityECE 353Introduction to Microprocessor SystemsMichael J. SchulteWeek 11Administrative MattersHomework #5 due Monday, April 28thQuiz #3 on Thursday, May 1st in 3534 EH from 7:15 to 8:30. Covers Module 5 and first half of Module 6 (weeks 9, 10, and 11)Similar in format to previous quizzesLook over education objectivesReview on Monday, April 28th from 5:30PM to 7:00PM in 2534 Engineering Hall.Reading for week 11 (interrupts and exceptions)Textbook chapter 8ADuC 74-75ARM7 2.8-2.10Quiz2 DataHigh: 91%, Low: 53%Avg: 64%, Median: 61%Grade Breakdown for midterm73-100 A63-72.9 AB58-62.9 B55-57.9 BC50-54.9 CTopicsInterrupt ConceptsARM7TDMI Interrupt HandlingADuC7026 Interrupt ImplementationInterrupt SourcesInterrupt Service Routines (ISRs)Interrupt Driven SystemsSoftware Interrupts and ExceptionsInterrupt Priority and LatencyDebugging Interrupt Hardware and SoftwareWhy Use Interrupts?Maximize processor utilization and efficiencyAllow use of sleep/idle states when nothing to do to save powerMinimize latency in responding to complex input/output structuresFacilitate event-driven applications and preemptive multitaskingWhat is hard about interrupts?Interrupt PrimerTerminologyBasic interrupt hardware (simple diagram)Interrupt request (IRQ)Interrupt acknowledge (INTA or IACK)Interrupt maskingMaskable interruptNon-maskable interrupt (NMI)Interrupt sensitivityLevel-sensitiveEdge-sensitiveInterrupt ConceptsSupporting multiple interrupt sourcesPolled interrupts – single ISRVectored interruptsFixed ISR locationsVector table implementationsGeneric implementationPrioritizationFixedRotatingHierarchicalSoftware interrupts and exceptionsARM7TDMI Interrupt HandlingInterrupt modesIRQBanks R13, R14, SPSRFIQBanks R8-R12, R13, R14, SPSRSWI (software interrupt) discussed laterInterrupt controlCPSR I/F flagsInterrupt processing sequenceInterrupt nestingADuC7026 Hardware InterruptsInterrupt sourcesInternal peripheralsExternal IRQ pinsProgrammed interruptsInterrupt sources can be individually programmed to generate either FIQ or IRQ mode entry.No prioritization of individual sources at a given levelADuC7026 Interrupt MMRsThese MMRs are used to control the interrupt handlingIRQSTA, FIQSTAOnes indicate that the sources have an interrupt enabled and pendingUsed in ISR to determine which device(s) needs serviceIRQSIG, FIQSIGOnes indicate that the source has an interrupt pendingIRQEN, FIQENOnes indicate that the interrupt request from the source is unmasked (i.e. the interrupt source is enabled)IRQCLR, FIQCLRWrite ones to clear the corresponding bit in IRQEN, FIQEN (i.e. mask an interrupt source)ADuC7026 Programmed InterruptsThe programmed interrupt feature allows us to programmatically force an entry into FIQ mode or IRQ modeWrite to SWICFG register, do not need to have programmed interrupt enabled in IRQEN/FIQENNote that the use of “SWI” has nothing to do with the ARM7 SWI instruction and supervisor modeInterrupt Service RoutinesISR prerequisitesaduc7026.sISR implementationContext saveClear IRQ from interrupt sourceAllow nesting (if desired)Handle interruptContext restoreReturn from interrupt/exceptionInterrupt Checklist on course web pageShared procedures and resourcesInterrupt Driven SystemsForeground vs. background tasks.Events determine the actual order of execution.InitializationMain ProgramLoopISRcISRbISRaSoftware Interrupts & ExceptionsSWI instructionExceptionsARM7TDMI exceptionsPrefetch abortData abortUndefined instructionResetOther common exceptionsDivide errorSingle-stepBreakpointInterrupt Prioritization and LatencyHandling multiple simultaneous interrupts and exceptionsARM7TDMI exception prioritiesInterrupt prioritization schemesFixedRotatingTiered (hierarchical) Interrupt LatencyDefinitionADuC7026 latency specificsInterrupt IssuesUsing periodic interrupts to perform iterative tasksWhat to do when good interrupts go bad…Software debuggingHardware debuggingReal-time issuesInter-process communication (IPC) issuesIn-Class Assessment QuizWhat sort of safeguards might you need to design into NMI hardware?For the ARM7TDMI, describe what happens between an IRQ being asserted and the actual execution of the ISR.What are the differences between vectored interrupts and polled interrupts?In-Class Assessment QuizWhat is a ‘level-sensitive’ interrupt?What problems could arise when using a semaphore to control access to a resource used by the main program and an ISR? What ARM7TDMI instruction(s) help handle this issue?What advantages does the FIQ interrupts have over IRQ interrupts in the ARM7?Wrapping UpReading for week 12Textbook 7.6-7.10Supplement #5 (Learn@UW)Interrupt TerminologyEventAsynchronous eventPending interruptInterrupt service routine (ISR)Interrupt driven I/OCritical code sectionInterrupt Processing SequenceCPU recognizes the interruptComplete execution of current instructionSave the current processor contextModify CPSR for IRQ/FIQ mode entryExecute IRQ/FIQ mode exception handlerReturn to execution of interrupted codeGeneric ImplementationG I EI E RI F RF FD e v i c e# 1F FD e v i c e# 2F FD e v i c e# 3F FD e v i c e# 4C P UI R Q 0I R Q 1I R Q 2I R Q 3Priority Interrupt ControllerARM7 CPSRCurrent Process Status Register (CPSR)Condition code flags (N, Z, C, V)Interrupt disable bits (I, F)Thumb mode enable (T)Never change directly!Mode selectThese bits cannot be changed in User mode31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0N Z C V reserved I F T modeARM7 SPSRSuspended Process Status Register (SPSR)SPSR is only present when


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UW-Madison ECE 353 - ECE 353 Week 11 Notes

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