ECE 353 Introduction to Microprocessor SystemsAdministrationQuiz #3 DataTopicsSerial I/O ConceptsSerial Communications Concepts - Morse CodeAsynchronous vs. SynchronousAsynchronous Data TransferUARTsUART InterruptsCircular BufferingRS-232Flow ControlADuC7026 Serial PeripheralsADuC7026 UARTADuC7026 SPI PortADuC7026 I2C PortsAsynchronous Communications - RS232 FramingSynchronous CommunicationsClock RecoverySerial Communications StandardsRS-232 ConnectorsRS-232 Signal LevelsMAX221Basic UART ConstructionECE 353Introduction to Microprocessor SystemsMichael SchulteWeek 13AdministrationHomework #6 due Friday, May 9thReading for week 13 (serial I/O)Textbook Chapter 10ADUC p. 62-71Supplement #4 (Learn@UW)Final exam on Saturday, May 17th from 7:45am to 9:45am in 3418 EHCumulative exam covering Modules 1-6 + Serial I/O (week 13)Review this FridayQuiz #3 returnedQuiz #3 DataHigh: 92%, Low: 66.5%Avg: 79%, Median: 80%Grade Breakdown for Quiz #385-100 A80-84.9 AB75-79.9 B70-74.9 BC65-69.9 CTopicsSerial I/OSerial data transfer concepts Asynchronous and synchronous transfersUARTsUART InterruptsCircular bufferingRS-232 and flow control ADuC7026 Serial PeripheralsUARTSPII2CSerial I/O ConceptsSerial communication transmits data one bit at a time.Why?Data transfers over long distancesReduced pin and interconnection countEasier to route with switchesEliminates parallel bus skew issuesTerminologyCommunications channelSimplex vs. duplex vs. half-duplexTransmission rates (baud rate vs. bit rate)Information codesData FramesSerial Communications Concepts -Morse CodeA .- N -. 1 .---- . .-.-.-B -... O --- 2 ..--- , --..--C -.-. P .--. 3 ...-- ? ..--..D -.. Q --.- 4 ....- ( -.--.E . R .-. 5 ..... ) -.--.-F ..-. S ... 6 -.... - -....-G --. T - 7 --... " .-..-.H .... U ..- 8 ---.. _ ..--.-I .. V ...- 9 ----. ' .----.J .--- W .-- 0 ----- : ---...K -.- X -..- / -..-. ; -.-.-.L .-.. Y -.-- + .-.-. $ ...-..-M -- Z --.. = -...-Asynchronous vs. SynchronousAsynchronous CommunicationNo common clock signal between transmitter and receiverSynchronization must be established on a per frame basisExample – RS232Synchronous CommunicationClock is transmitted in addition to data, or is recovered from data signalOften includes a framing signal as wellExample – I2SAsynchronous Data TransferRS-232 signal phasesIdleStart bitDataParityStop bitIdle or Start next frameS T A R TD 0 D 1 D 2 D 3 D 4 D 5 D 6 PS T O PI D L EI D L E o rS T A R TUARTsUniversal Asynchronous Receiver-TransmitterBasic UART constructionPractical UARTsComplex I/O device functionality encapsulated behind a register interfaceControlStatusDataFIFOsMODEM control signalsUART InterruptsUARTs often can generate interrupts for a number of conditionsReceive data readyReceive data errorFraming, parity, overrunModem signal status changesTransmitter buffer emptyIf data available, just sent itIf no data available and level sensitive interrupts, ISR should mask the transmit interrupt and the program putting data in the queue should unmask itCircular BufferingImplement simple FIFO queueing in software to minimize data movement.Some CPUs (especially DSPs) implement circular addressing modes in hardware for speed.RS-232RS-232 is one of many physical-level standards for serial communications.Selected serial communications standardsRS-232 defines many aspects of the serial data channelEquipment definitionsConnector construction and pin-outsModem control signalsSignal levelsRS-232 line drivers and receiversFlow ControlA serial channel may deliver data faster than the receiving device can process.Flow control gives the receiver a way to signal the transmitter to stop transmission.Flow control can be implemented asSoftwareXON/XOFF flow control protocolHardwareRTS/CTSADuC7026 Serial PeripheralsThere are 4 serial peripherals on the ADuC7026; a UART and 3 synchronous ports (SPI and I2C)There are ten pins that are used by the serial peripherals in two modesADuC7026 UARTCOMCON0Basic frame configurationBaud rateBasic baud rate dividerFractional baud rate dividerADuC7026 SPI PortThe Serial Peripheral Interface (SPI) port can be configured as a master or slave (shown below)SPI consists of 2 unidirectional data lines, a clock line, and a chip select lineADuC7026 I2C PortsThe Inter-Integrated Circuit (I2C) ports can operate as master or slaveI2C supports multi-master buses using just 2 bidirectional lines (clock and data)Both use open-drain drivers and pull-up resistorsCollisions can occur without damage – recognized when a line will not return high after it is releasedAsynchronous Communications -RS232 FramingBackWhat do you need to know in order to figure out what the data is?When should the data be sampled?Synchronous CommunicationsBackframeClock RecoveryBack11 1 1 1 1 10 0+V-V+V-V1011 1 1 1 1 10 0 Raw dataRZ, bipolar1 1 1 1 1 1 100 NRZ, ManchesterSerial Communications StandardsBackRS-232 ConnectorsBackRS-232 Signal LevelsBackData signals are shown. Control signals have opposite polarity.MAX221BackBasic UART ConstructionTransmitterReceivershift registerclockdata holding registercontrolunitloadserial data outdata1data bus/wrloadserial data inshif tshift registerdatadata holding registerloadcontrolunitdata bus/rdshif tdavreadyclock routing not shown for
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