ECE 353 Introduction to Microprocessor SystemsAdministrativeTopicsBasic System Bus OperationADuC7026 Bus OperationADuC7026 DemultiplexingSRAM Timing CompatibilityAssessing Timing CompatibilityAddress Valid to Data Valid Time (tAvdv)System Timing CompatibilityAnalyzing the address access time (tAA)Analyzing the chip enable access time (tCE)Analyzing the output enable access time (tOE)Analyzing the data float time (tDF)ADuC7026 External Memory Interface ConfigurationADuC7026 GPIO PortsADuC7026 XMxCONADuC7026 XMxPARSlide 19Timing Wrap-UpWrapping UpBasic Read CycleBasic Write CycleRead Cycle ParametersWrite Cycle ParametersRead Cycle ControlsWrite Cycle Controls16-Bit Memory SystemECE 353Introduction to Microprocessor SystemsMichael J. SchulteWeek 10AdministrativeReading for next week 10Supplement #3, review chapter 9 in text, ADuC datasheet pages 79-82Homework #4 returnedAverage of 85%Still grading Quiz #2TopicsADuC7026 External Memory InterfaceImplementationDemultipexingBus TimingBus cycle timing modificationWait states and moreAssessing timing compatibilityBasic System Bus OperationAddressUnidirectional from CPUDataBidirectionalControl/RS or /RD – output from CPUIndicates a read operation in progress/WS or /WR – output from CPUIndicates a write operation in progress/WAIT or /READY – input to CPUUsed by external device to signal that it is not able to complete transfer yetADuC7026 Bus OperationThe ADuC7026 external memory interface consists of16-bit multiplexed address/data bus (AD15:0)High address for 8-bit operation (A16)Read and write strobes (/RS, /WS)Memory select signals (/MS3:0)Byte enables (/BHE, /BLE)Demultiplexing control signal (AE)There is no WAIT/READY signalBasic Read Cycle Sequence at Bus LevelDiagramBasic Write Cycle Sequence at Bus LevelDiagramADuC7026 DemultiplexingMultiplexed Signal TimingRead CycleDealing with a multiplexed busDemultiplexing by the deviceDemultiplexing logic to create an address busImplementationDevices – latches or flip-flopsConnectionsAE timingSRAM Timing CompatibilityIn order to properly read and write the device, we need to ensure that the processor-to-memory interface is compatible with the memory device.This is accomplished by analyzing the timing for all relevant parameters, and ensuring that the operation can be completed successfully.We will work through the read cycle analysis for the ADuC7026...Assessing Timing CompatibilityNeed to know whether CPU could operate with the tAA for given device. (read cycle)We designate a CPU characteristic tAVDV, which is the delay fromWhen the address becomes valid at the CPUUntil the data must be driven to CPUThis establishes an upper bound on tAAtAA < tAVDVRead cycle parameters (see handout) Read cycle timing control (see handout)Simple ExampleAddress Valid to Data Valid Time (tAvdv)If the fastest bus cycle is used then tAVDV = 3 CLK - tDATA_SETUP If the bus cycle is extended then tAVDV = 3 CLK - tDATA_SETUP + (nAW + nAH + nRDTA + nW) CLK address wait states (nAW) – set by XMxPAR[14:12] (0-7)address hold time (nAH) – set by XMxPAR[10] (0-1)read turn-around time (nRDTA) – set by XMxPAR[9] (0-1)wait states (nW) – set by XMxPAR[3:0] (0-15)There is an upper bound on tAAtAA < tAVDVSystem Timing CompatibilityNeed to account for all delays in a system to assess timing compatibility.Consider this system.Analyze the read timing with regard to:tAA – address access timetACS – chip enable to valid datatOE – output enable to valid datatDF – output hold/float timeRead cycle timing control (see handout)Information also in Supplement 3Analyzing the address access time (tAA) Before a valid address is available at the SRAM, it must and go through the latch after ½ clock cycle . This givestAA < tAVDV - ½PCLK – tLATCHExpanding tAVDV givestAA < 2.5 CLK - tDATA_SETUP - tLATCH + (nAW + nAH + nRDTA + nW) CLKAnalyzing the chip enable access time (tCE) The chip enable depends on /MSx, /BHE, /BHE and the address The last signal to arrive at the decoder is the byte enablesThe byte enables are asserted one cycle before the rising edge of /RS, which givestCE < CLK - tDATA_SETUP – tDECODERIf the read cycle is lengthened thentCE < CLK – tDATA_SETUP – tDECODE_LOGIC + (nAH + nRDTA + nW) CLKWhat happens for an 8-bit bus (no byte enables)?Analyzing the output enable access time (tOE) The SRAM /OE input is driven by the /RS signalFor the fastest bus cycle this givestCE < CLK – tDATA_SETUPIf the read cycle is lengthened thentCE < CLK – tDATA_SETUP + (nW) CLKAnalyzing the data float time (tDF) How long is the data guaranteed to be valid? Will it meet the hold time? The data may go invalid if the address becomes invalid, or \CS or \OE go high. Which occurs first?Based on the read cycle parameters, we must guaranteetOHZmin > tDATA_HOLD To ensure the SRAM stops driving before the processor drives the next address, we need tOHZMAX < CLKADuC7026 External Memory Interface ConfigurationThe external memory interface supports four independently configured memory regions, each of which is 128kB in size.In order to use the external memory interface, we need toConfigure the required pins (GPxCON)Enable the external interface (XMCFG[0] = 1)Configure for bus width and enable the region (XMxCON)Configure for the desired bus timing (XMxPAR)ADuC7026 GPIO PortsThe ADuC7026 has 40 pins organized as 5 ports that can be used as digital GPIOAll pins have multiple functions in addition being able to be used as GPIOThe configuration selection is set through the GPxCON MMR.ADuC7026 XMxCONThe XMxCON registers configure the bus width and enable the interface for the respective 128KB memory region.XM0CON  0x10000000-0x1001FFFFXM1CON  0x20000000-0x2001FFFFXM2CON  0x30000000-0x3001FFFFXM3CON  0x40000000-0x4001FFFFADuC7026 XMxPARThe XMxPAR MMR configures the bus timing for a region0x70FF at reset[14:12] – AE extend[9] – implements bus turn-around[8] – provides additional hold time [7:4],[3:0] – extend write/read strobesWrite cycle timing controlRead cycle timing controlSystem Timing CompatibilityConsider again the system.Analyzing write cycle timing.SRAM write characteristicstWCtAS, tAW, tCWtWR tWDS, tWDHWrite cycle controlsTiming Wrap-UpDevice characteristics are just part of the total timing analysis pictureLine/device capacitive loading and