Department of Electrical and Computer Engineering University of Wisconsin-Madison ECE 353/315 ARM7TDMI Instruction Set Reference Michael G. Morrow 2009Last updated 10/8/2009 4:43 PMi Table of Contents 1 Instruction Encoding ............................................................................................................................................ 1 1.1 ARM7TDMI – ARM Instructions .............................................................................................................................. 1 1.2 ARM7TDMI – THUMB Instructions .......................................................................................................................... 2 2 Conditional Execution ........................................................................................................................................... 2 2.1 Condition Field ...................................................................................................................................................... 2 2.2 Condition Codes .................................................................................................................................................... 2 3 Addressing, Operands and Directives ................................................................................................................... 3 3.1 General Notes ....................................................................................................................................................... 3 3.2 Shifter Operands ................................................................................................................................................... 3 3.3 Load/Store Register Addressing Modes ................................................................................................................... 6 3.4 Miscellaneous Load/Store Addressing Modes ........................................................................................................... 8 3.5 Memory Allocation and Operand Alignment ............................................................................................................. 9 3.6 Miscellaneous Assembler Directives ....................................................................................................................... 10 4 Instruction Descriptions ..................................................................................................................................... 12 4.1 General Information ............................................................................................................................................. 12 4.2 ADC – Add with Carry ........................................................................................................................................... 12 4.3 ADD - Add ........................................................................................................................................................... 13 4.4 AND – Bit-wise AND ............................................................................................................................................. 13 4.5 B, BL – Branch, Branch and Link ........................................................................................................................... 14 4.6 BIC – Bit Clear ..................................................................................................................................................... 15 4.7 BX – Branch and Exchange ................................................................................................................................... 15 4.8 CMN – Compare Negative ..................................................................................................................................... 16 4.9 CMP - Compare .................................................................................................................................................... 16 4.10 EOR – Bit-wise Exclusive-OR ................................................................................................................................. 17 4.11 LDM – Load Multiple ............................................................................................................................................. 17 4.12 LDR – Load Register ............................................................................................................................................. 19 4.13 LDRB – Load Register Byte ................................................................................................................................... 20 4.14 LDRH – Load Register Halfword ............................................................................................................................ 20 4.15 LDRSB – Load Register Signed Byte ...................................................................................................................... 21 4.16 LDRSH – Load Register Signed Halfword ............................................................................................................... 21 4.17 MLA – Multiply-Accumulate ................................................................................................................................... 22 4.18 MOV – Move ........................................................................................................................................................ 22 4.19 MRS – Move PSR into General-Purpose Register ..................................................................................................... 23 4.20 MSR – Move to Status Register from ARM Register ................................................................................................ 23 4.21 MUL – Multiply ..................................................................................................................................................... 24 4.22 MVN – Move Negative .......................................................................................................................................... 25 4.23 ORR – Bit-wise Inclusive-OR ................................................................................................................................. 25 4.24 RSB – Reverse Subtract