ECE 353 Introduction to Microprocessor SystemsTopicsLook-Up TablesLUT ExamplesBranchesConditional Branches and LoopingImplementing Structured Programming ConstructsStack ImplementationARM7TDMI Stack OperationWrapping UpSP Init Disassembly DumpPIC16F84 Hardware StackJump TablesHardware for Sample ProgramB Instruction ReferenceBL Instruction ReferenceBX Instruction ReferenceDisassembly FragmentECE 353Introduction to Microprocessor SystemsMichael G. Morrow, P.E.Week 5ARM7TDMI ProgrammingLUTsBranches and LoopsStructured ProgrammingFlowchartsStacksHardware versus Memory StacksARM7TDMI Stack ManagementTopicsLook-Up TablesIn an embedded system, the code area is usually in nonvolatile memory (ROM)Data in the code area will also be placed in ROM – so the data is constantLook-up tables (LUTs) are used to translate a value from one domain to another when…There is no convenient mathematical relationship between the two domainsThe calculations are too expensive for the application constraintsLUT ExamplesExercises: Write code fragments that… 1. Use a lookup table to get a 32-bit mask that will be used to clear individual bytes as directed by a 4-bit value (i.e. 2_1001 means that we want to clear the middle two bytes and preserve the most/least significant bytes)2. Use a lookup table to get the square root of an unsigned half-word valueDisassembly fragmentIn both cases, Assume that the value to convert is in R0, and place the result in R1Identify how large the complete data table will beBranchesBranches redirect program flow by loading a new PC valueIn many processors, a branch that does not return is called a jumpARM7TDMI branch instructionsB target_addressTarget_address is a labelInstruction encodes a signed 24-bit offsetBX <Rm>Branch address is in a registerCan be used to jump to Thumb codeJump tablesBe sure index is bounds-checked!Conditional Branches and LoopingConditional branches allow program flow to change in response to conditionsAction is based on current state of flagsPrior instruction must be used to set flagsCan use backwards conditional jumps to create a loop that can be terminated -By a conditionAfter a predetermined number of iterationsOr a combination of bothLooping examples Incrementing loopsDecrementing loopsImplementing Structured Programming ConstructsStructured programming basicsOne entry point, one exit point per subroutineBased on three basic control structuresSequenceSelectionIf, If/Else, Switch/CaseRepetitionWhileDo-WhileFlowchart BasicsProgramming ExerciseStack ImplementationThe stack is a LIFO data structureWhat is the stack used for?Two basic stack operationsPUSHPOP (aka PULL)Hardware stacks vs. memory stacksHardware stackMemory stackStack pointer (SP)Stack topologies and SP operationARM7TDMI Stack OperationBy convention, the stack pointer is R13ARM stack terminologyEmpty versus fullAscending versus descendingAllocating stack spaceSP initializationStack operationsLDR/STRLDM/STMPUSH/POPARM operating modes and stacksWrapping UpHomework #3 is due Friday, 3/7Quiz #1 will be held Wednesday, 2/27 at 7:15pm in room 2345 EH.Coverage will be over modules 1 and 2. Calculators are not permitted. You may have a 3x5 card with handwritten notes. The instruction set documentation will be provided. If you have a conflict, please send me the details by email.SP Init Disassembly Dump24: LDR R13, =(Stack_Mem) EA0x000800F4 E59FD058 LDR R13,[PC,#0x0058]25: LDR R13, =(Stack_Top-4) ED0x000800F8 E59FD058 LDR R13,[PC,#0x0058]26: LDR R13, =(Stack_Mem-4) FA0x000800FC E59FD058 LDR R13,[PC,#0x0058]27: LDR R13, =(Stack_Top) FD0x00080100 E59FD058 LDR R13,[PC,#0x0058]..0x00080154 00010000 DD 0x000100000x00080158 000100FC ???EQ 0x0008015C 0000FFFC ???EQ 0x00080160 00010100 ANDEQ R0,R1,R0,LSL #2PIC16F84 Hardware StackJump Tablesstart MOV R0, ??? ; assume index is in R0 MOV R1, jmptbl ; get base address LDR R0, [R1,R0,LSL #2] ; do look-up BX R0 ; branch to target;task0 ; stub NOP B start;task1 ; stub NOP B start;jmptbl DCD task0, task1; ...Hardwarefor Sample ProgramB Instruction ReferenceSyntaxB{<cond>} <target_address>RTLif (cond is true) PC PC + offsetFlags are not affected31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0cond 1 0 1 0 signed_immediate_24BL Instruction ReferenceSyntaxBL{<cond>} <target_address>RTLif (cond is true) R14 next instruction addressPC PC + offsetFlags are not affected31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0cond 1 0 1 1 signed_immediate_24BX Instruction ReferenceSyntaxBX{<cond>} <Rm>RTLif (cond is true) T flag Rm[0]PC Rm & 0xFFFFFFFEFlags are not affectedIn ARM v5 and higher, there is also a BLX instruction31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0cond 0 0 0 1 0 0 1 0 SBO SBO SBO 0 0 0 1 RmDisassembly Fragment 57: ADR R2, sqrt_LUT0x00080104 E24F2024 SUB R2,PC,#0x00000024 58: LDR R1, sqrt_MASK 0x00080108 E51F1020 LDR
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