Verilog for Digital DesignChapter 2: Combinational Logic DesignVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky1AND/OR/NOT GatesAND/OR/NOT GatesVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky2AND/OR/NOT GatesVerilog Modules and PortsVerilog Modules and PortsYXFYXFXFmodule And2(X, Y, F);input X, Y;output F;module Or2(X, Y, F);input X, Y;output F;module Inv(X, F);input X;output F;•module–Declares a new type of componentp;...p;...p;...moduleDeclares a new type of component– Named “And2" in first example above– Includes list of ports (module's inputs and outputs)• input – List indicating which ports are inputs• output – List indicating which ports are outputs • Each port is a bit – can have value of 0, 1, or x (unknown value)• Note: Verilog already has built-in primitives for logic gates, but instructive to build themVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky3vldd_ch2_And2.v vldd_ch2_Or2.v vldd_ch2_Inv.vAND/OR/NOT GatesModules and PortsModules and PortsYXFYXFXFmodule And2(X, Y, F);input X, Y;output F;module Or2(X, Y, F);input X, Y;output F;module Inv(X, F);input X;output F;• Verilog has several dozen keywords– User cannot use keywords when naming items like modules or ports – module, input, and output are keywords aboveKeywords must belower casenot UPPER CASE or a MixTure thereof.........–Keywords must be lower case, not UPPER CASE or a MixTure thereof• User-defined names – Identifiers– Begin with letter or underscore (_), optionally followed by any sequence of letters, digits, underscores, and dollar signs ($)–Valid identifiers:A,X,Hello,JXYZ,B14,Sig432,Wire 23,F1, F$2, Go $ $, , InputValid identifiers: A, X, Hello, JXYZ, B14, Sig432, Wire_23, _F1, F$2, _Go_$_$, _, Input• Note: "_" and "Input" are valid, but unwise– Invalid identifiers: input (keyword), $ab (doesn't start with letter or underscore), 2A (doesn't start with letter or underscore)• Note: Verilog is case sensitive. Sig432 differs from SIG432 and sig432Verilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky4– We'll initially capitalize identifiers (e.g., Sig432) to distinguish from keywordsvldd_ch2_And2.v vldd_ch2_Or2.v vldd_ch2_Inv.vAND/OR/NOT GatesModules and PortsModules and Ports• Q: Begin a module definition for a 4x1 multiplexor – Inputs: I3, I2, I1, I0, S1, S0. Outputs: DI0Mux4I0I2I1I3S1S0Dd l M 4(I3 I2 I1 I0 S1 S0 D)S1S04x1 muxmodule Mux4(I3, I2, I1, I0, S1, S0, D);input I3, I2, I1, I0;input S1, S0;output D;......Note that input ports above are separated into two declarations for clarityfyVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky5vldd_ch2_Mux4Beh.vAND/OR/NOT GatesModule Proceduresalways Module Procedures—always • One way to describe a module's behavior uses an "always" procedure–always–Procedure that executes repetitivelyxFalwaysProcedure that executes repetitively (infinite loop) from simulation start–@– event control indicating that statements should only execute when values change•"(X,Y)"–execute if X changes or Y changesyFmodule And2(X, Y, F);(X,Y) execute if X changes or Y changes (change known as an event)• Sometimes called “sensitivity list”• We’ll say that procedure is “sensitive to X and Y”– "F <= X & Y;" – Procedural statement that sets wait until X or Y changes(, , )input X, Y;output F;reg F;l@()biF to AND of X, Y•&is built-in bit AND operator•<=assigns value to variable–reg– Declares a variable data type, which F <= x AND yalways @(X, Y) beginF <= X & Y;endendmoduleholds its value between assignments• Needed for F to hold value between assignments• Note: "reg", short for "register", is an unfortunate name A reg variable may or may notvldd_ch2_And2.vVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky6name. A reg variable may or may not correspond to an actual physical register. There obviously is no register inside an AND gate.AND/OR/NOT GatesModule Proceduresalways Module Procedures—always • Q: Given that "|" and "~" are built-in operators for OR and NOT, complete the modules for a 2-input OR gate and a NOT gateyxFxFmodule Or2(X, Y, F);input X, Y;output F;module Inv(X, F);input X;output F;reg F; reg F;always @(X, Y) beginF <= X | Y;endendmodulealways @(X) beginF <= ~X;endendmoduleendmoduleendmoduleVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky7vldd_ch2_Or2.v vldd_ch2_Inv.vAND/OR/NOT GatesSimulation and Testbenches A First LookSimulation and Testbenches —A First Look• How does our new module behave?•Simulation•Simulation– User provides input values, simulator generates output values• Test vectors – sequence of input valuesTimescale directive is for simulation. More later.• Waveform – graphical depiction of sequence`timescale 1 ns/1 nsmodule And2(X, Y, F);input X, Y;ttF10XUser provides test toutput F;reg F;always @(X, Y) beginF <= X & Y;endY10vectorsF1Simulator generates output values based endendmoduletime0pon HDL descriptionSi l tVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky8Simulatorvldd_ch2_And2.vAND/OR/NOT GatesSimulation and Testbenches A First LookSimulation and Testbenches —A First Look• Instead of drawing test vectors, user can describe them with HDLcan describe them with HDL`timescale 1 ns/1 ns10X...Y_s <= 0; X_s <= 0;#10 0 1module And2(X, Y, F);input X, Y;output F;reg F;0Y10time()102030#10 Y_s <= 0; X_s <= 1;#10 Y_s <= 1; X_s <= 0;#10 Y_s <= 1; X_s <= 1;...always @(X, Y) beginF <= X & Y;endendmoduleF10(ns)102030endmodule"#10" –Tells simulator to keep present values for 10 ns, before executing the next statementVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky9Simulatorvldd_ch2_And2.vAND/OR/NOT GatesSimulation and Testbenches`timescale 1 ns/1 nsIdea: Create new "Testbench" module that provides test vectors to component's inputstimescale 1 ns/1 nsmodule Testbench();reg X_s, Y_s;wire F s;TestbenchCompToTest (A d2)XFX_sYsF_sedure•HDLtestbenchwire F_s;And2 CompToTest(X_s, Y_s, F_s);initial begin// Test all possible input combinations (And2)YFY_s_proc•HDL testbench– Module with no ports– Declare reg variable for each input port, wire for each output portY_s <= 0; X_s <= 0;#10 Y_s <= 0; X_s <= 1;#10 Y_s <= 1; X_s <= 0;#10 Y_s <= 1; X_s <= 1;end– Instantiate module, map variables to ports (more in next section)– Set variable values at