ECE 5440/6370Instructor: Dr. Y. ChenTA: Yiyong Zha2Fb20102-Feb-2010What are they?What are they? ModelSim: a compliant Verilog simulator toolTo verify the designTo verify the design Quartus II: the FPGA Vendor toolTo synthesize the designTo synthesize the design To program the boardtest benchti lDesignTeststimulusDesignoutputssynthesizableun-synthesizabletest benchstimulusDesignTestoutputstest benchstimulusDesignTestoutputsModelSim-Altera starter editionhttps://www.altera.com/support/software/download/eda_software/dli /id jmodelsim/msm-index.jspQuartus II web editionhttps://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jspUSB-Blaster Driverhttp://www.altera.com/support/software/drivers/dri-index.htmlGet startedGet startedCkilibCreate a working libraryCompile design filesLoad and Run simulationDebug resultsCr t pr j tCreate a projectAdd files to the projectAdd files to the projectCompile design filesCompile design filesRun simulationRun simulationDebug resultsgCreate a new project.Type in the project name.Add the source file(s) to the project by clicking “Add” and selecting the specific file(s).Click edit to view the source files.Click Compile to compile the source file or you can click Compile All to compile all the source files in the project.If there shows no error after compiling, we can start the simulation. Otherwise we need to fix the errorMake sure you choose the right module.First click the Objects button and then add all the signals to wave.First click the Wave button and then run the simulation.Setup the projectSetup the project.Create a new project.A introduction page will pop-up. Click next to continue.Set the working directory.Name the project.Specify the top-level entity. (Case sensitive)Add source files to the project.Select synthesizable codes.Select the device. (family Cyclone and model # EP2C35F672C6)Use the filter to quickly locate the device.Specify other EDA tools. (Select VCS as the simulation tool.)A short summary.You can go back if you spot anything wrong.Set timing constraintsSet timing constraints.All designs need to run at a specified clock speed. Designers can make the settings under the Assignment menu.This wizard allows you to make the timing constraints you need for the device.Click yes to specify the default frequency.For some applications, setup time/hold time/etc should be specified too.Enter the clock frequency (50MHz).The wizard also takes you through making other time requirements.For out projects, we can use the default settings.Finally, a summary page lets you know the settings you have made.Click finish to proceed.Compile the projectCompile the project.Click open to view and edit the source files.Start compilation by clicking the Purple “buffer”. And wait for completion……Flow summary.Assign the PinsAssign the Pins.Assign Pins.Type in the location for each input/output pin.Pin information is available in the DE2 user manual. Save this file.Assign the Output PinAssign the Output PinLoad (optional).Load (optional).Assign the output pin load for every output pin.Open the Assignment Editor located under the Assignment menu.In the Category field, choose I/O Features.Use the node finder to find all the output pins first.Specify “Pin: output” to filter and launch “List”.Select all the assigned output nodes by clicking “>” button.The selected nodes now appear here in the list.For the Assignment Name field, select “Output Pin Load”.For the Value field, type in a typical value “10”.Do the same for all the pins.Save and redo the compilation.Note: Before powering up the board make sureNote: Before powering up the board, make sure the switch is placed on “PROG” side.Start programming.Specify the programming mode (Active Serial Programming).Specify the programming file (file extension .pof).Click “Start” to program the board.Wait patiently until the progress showing is 100%.Now you can turn the switch to the“RUN”sideNow you can turn the switch to the RUN side. Mission completed and Enjoy.Test bench is a virtual environment used toTest bench is a virtual environment used to verify the correctness or soundness of a design. Top-level module that contains both the design core pg(under test) and test module.  Silos is for debugging and verification purpose. Test bench approach used  Quartus is to synthesize the verified design and to program FPGA. only synthesize the design