5440/6370 Lab 1 due on Feb 26th, 2010 at 11:59 pm (dropfolder submission) Switches, Lights, and Multiplexers The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these devices. We will use the switches SW17−0 on the DE2 board as inputs to the circuit. We will use light emitting diodes (LEDs) and 7-segment displays as output devices. Instruction: You are to form a 3-person lab team to complete Lab 1 (and all other lab assignments) Deliverables: (i) Synthesizable RTL Verilog code for the lab1 circuit (Part I and Part II). (ii) Behavioral Verilog test bench code for testing the correct operation of the lab1 circuit that provides stimulus for the lab1 circuit device that will input various values to the circuit, (iii) Waveforms (electronic jpg pictures preferred) demonstrating the correct behavior of the circuit captured from the ModelSim waveform viewer obtained from the test bench. (iv) Board demonstration to the TA. Demonstration is to be done AFTER you have finished and submitted your deliverables to the dropfolder. You will have until March 5th, 2010 to demonstrate to TA during normal TA lab hours. You are only allowed to use the code downloaded from dropfolder for demonstration. No new code is allowed!!! Submission: All submissions should be deposited in the assignments folder via dropfolder. Only one submission from each team is needed. Make sure that when you submit your code via dropfolder, you follow the naming convention below: Example: Top level folder name: Lab1_Team1_LastNameOfTeamLeader Under the top folder, include 1) a README file which includes the team member info (name, peoplesoft ID, email address for each team member) 2) PartI folder: Include TWO folders: One for your Verilog source code, and one for an archive of your QUARTUS II file (.qar file). 3) PartII folder: Include THREE folders. One for your Verilog source code, one for your ModelSim project files, and one for an archive of your QUARTUS II files (.qar file). This is VERY important. If the TA has to build your projects to run the simulation you will lose BIG points! Part I The DE2 board provides 18 toggle switches, called SW17−0, that can be used as inputs to a circuit, and 18 red lights, called LEDR17−0, that can be used to display output values. Figure 1 shows a simple Verilog module that uses these switches and shows their states on the LEDs. Since there are 18 switches and lights it is convenient to represent them as vectors in the Verilog code, as shown. We have used a single assignment statement for all 18 LEDR outputs, which is equivalent to the individual assignments assign LEDR[17] = SW[17]; assign LEDR[16] = SW[16]; . . . assign LEDR[0] = SW[0]; The DE2 board has hardwired connections between its FPGA chip and the switches and lights. To use SW17−0 and LEDR17−0 it is necessary to include in your Quartus II project the correct pin assignments, which are given in theDE2 User Manual. For example, the manual specifies that SW0 is connected to the FPGA pin N25 and LEDR0 is connected to pin AE23. // Simple module that connects the SW switches to the LEDR lights module part1 (SW, LEDR); input [17:0] SW; // toggle switches output [17:0] LEDR; // red LEDs assign LEDR = SW; endmodule Figure 1. Verilog code that uses the DE2 board switches and lights. Perform the following steps to implement a circuit corresponding to the code in Figure 1 on the DE2 board. 1. Create a new Quartus II project for your circuit. Select Cyclone II EP2C35F672C6 as the target chip, which is the FPGA chip on the Altera DE2 board. 2. Create a Verilog module for the code in Figure 1 and include it in your project. 3. Include in your project the required pin assignments for the DE2 board. Compile the project. 4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by toggling the switches and observing the LEDs. Part II Figure 2a shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. If s = 0 the multiplexer’s output m is equal to the input x, and if s = 1 the output is equal to y. Part b of the figure gives a truth table for this multiplexer, and part c shows its circuit symbol. The multiplexer can be described by the following Verilog statement: assign m = (׽s & x) | (s & y);You are to write a Verilog module that includes eight assignment statements like the one shown above to describe the circuit given in Figure 3a. This circuit has two eight-bit inputs, X and Y , and produces the eight-bit output M. If s = 0 then M = X, while if s = 1 then M = Y . We refer to this circuit as an eight-bit wide 2-to-1 multiplexer. It has the circuit symbol shown in Figure 3b, in which X, Y , and M are depicted as eight-bit wires. Perform the steps shown below. 1, Simulate your design using Silos. 2. Create a new Quartus II project for your circuit. 3. Include your Verilog file for the eight-bit wide 2-to-1 multiplexer in your project. Use switch SW17 on the DE2 board as the s input, switches SW7−0 as the X input and SW15−8 as the Y input. Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG7−0. 4. Include in your project the required pin assignments for the DE2 board. As discussed in Part I, these assignments ensure that the input ports of your Verilog code will use the pins on the Cyclone II FPGA that are connected to the SW switches, and the output ports of your Verilog code will use the FPGA pins connected to the LEDR and LEDG lights. 5. Compile the project. 6. Download the compiled circuit into the FPGA chip. Test the functionality of the eight-bit wide 2-to-1 multiplexer by toggling the switches and observing the LEDs.