Verilog for Digital DesignChapter 1: IntroductionVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky1Digital SystemsDigital SystemsVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky2Digital Systems• Digital systems surround us– Electronic system operating on 0s and 1sT i ll i l t d I t t d Ci it (IC)–Typically implemented on an Integrated Circuit (IC) –"chip"• Desktop/laptop computers ("PCs") are the most popular examplespopular examples• Other increasingly common examples– Consumer electronics: Cell phones, portable music players, cameras, video game consoles, electronic iimusic instruments, ...– Medical equipment: Hearing aids, pacemakers, life support systems, ...–Automotive electronics: Engine control brakesAutomotive electronics: Engine control, brakes, ...– Military equipment– Networking components: Routers, switches, ... –Many, many more...Verilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky3yyHardware Description Languages (HDLs)Hardware Description Languages (HDLs)Verilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky4Digital Systems and HDLs100,00010,000IC (millions)• Typical digital components per IC– 1960s/1970s: 10-1,0001980 1 000100 0001,0001001070369258Transistors per I–1980s: 1,000-100,000– 1990s: Millions– 2000s: Billions •1970sInputs: b; Outputs: xOffx=0b’diagrams199720002003200620092012201520181970s– IC behavior documented using combination of schematics, diagrams, and natural language (e g English)Combinational LogicbOn2On1 On3x=1x=1x=1bschematicsnatural language(e.g., English)• 1980s– Simulating circuits becoming more importantCombinationallogicStateregisters1 s0n1n0xbclkFSMinputsFSMoutputsn1bx"The system has four states. When in state Off, the system outputs 0 and stays in state Off until the input p• Schematics commonplace• Simulating schematic helped ensure circuit was correct before costly implementationStateregisterclkn0s0s1clkState registerff pbecomes 1. In that case, the system enters state On1, followed by On2, and then On3, in which the system outputs 1 The system thenVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky5outputs 1. The system then returns to state Off."HDLs for Simulation• Hardware description languages (HDLs) –Machine-readable textuallanguages for describing hdFSM outputsFSM i t// CombLogicalways @(State B) beginhardware– Text language could be more efficient means of circuit entry than graphicalClk_sFSM inputsalways @(State, B) begincase (State) S_Off: beginX <= 0;if (B == 0) StateNext <= S_Off;elsecircuit entry than graphical language102030405070B_sX_sRst_s608090110100StateNext <= S_On1;endS_On1: beginX <= 1;StateNext <= S_On2;endS On2: beginSimulation102030405070608090110100S_On2: beginX <= 1;StateNext <= S_On3;endS_On3: beginX <= 1;StateNext <= S Off;Verilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky6_endendcaseendVerilogmodule DoorOpener(C,H,P,F);input C, H, P;output F;reg F;• Verilog– Defined in 1985 at Gateway Design Automation Inc., which was then acquired by Cadence Design Stalways @(C,H,P)beginF <= (~C) & (H | P);endendmoduleSystems – C-like syntax– Initially a proprietary language, but became open standard in early 1990s, then IEEE standard ("1364") in 1995, revised in 2002, and again in 2005.ENTITY DoorOpener ISPORT (c, h, p: IN std_logic;f: OUT std_logic);END DoorOpener;ARCHITECTURE Beh OF DoorOpener IS() , ,g• Other HDLs– VHDL • VHSIC Hardware Description Language / defined in 1980s / U.S. Dept. of Defense project / Ada-like syntax / IEEE standard ("1076") in 1987BEGINPROCESS(c, h, p)BEGINf <= NOT(c) AND (h OR p);END PROCESS;END Beh;IEEE standard ( 1076 ) in 1987• VHDL & Verilog very similar in capabilities, differ mostly in syntax– SystemC• Defined in 2000s by several companies / C++ libraries and macro routines / IEEE standard ("1666") in 2005#include "systemc.h"SC_MODULE(DoorOpener){sc_in<sc_logic> c, h, p;sc_out<sc_logic> f;SC CTOR(DoorOpener)and macro routines / IEEE standard ( 1666 ) in 2005• Excels for system-level; cumbersome for logic level– SystemVerilog• System-level modeling extensions to Verilog / IEEE Standard ("1800") in 2005_( p){SC_METHOD(comblogic);sensitive << c << h << p;}void comblogic(){f write(( c read()) & (h read() | p read()));Verilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky7f.write((~c.read()) & (h.read() | p.read()));}};HDLs for Design and SynthesisHDLs for Design and SynthesisVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky8HDLs for Design and Synthesis• HDLs became increasingly used for designing ICs using top-down design processHDLprocess– Design: Converting a higher-level description into a lower-level one– Describe circuit in HDL, simulateFSM outputsFSM i tClk_sRst_sHDL• Physical design tools automatically convert to low-level IC design– Describe behavior in HDL, simulate• e.g., Describe addition as A = B + C, FSM inputsSynthesisHDL behavior102030405070b_sx_s60 8090 110100rather than as circuit of hundreds of logic gates– Compact description, designers get function right first•Design circuitb_sx_sClk_sRst_sHDL circuit•Design circuit – Manually, or – Using synthesis tools, whichautomatically convert HDL behavior to HDL circuitSi l t i it h ld t h10203040507060 8090 110100Physical designVerilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky9–Simulate circuit, should matchHDLs for Synthesis• Use of HDLs for synthesis is growing– Circuits are more complex– Synthesis tools are maturing• But HDLs originally defined for simulationClk_sRst_sSimulate– General language– Many constructs not suitable for synthesisSynthesisHDL behavior102030405070b_sx_s60 8090 110100• e.g., delays– Behavior description may simulate, but not synthesize, or may synthesize to incorrect or inefficient circuitHDL circuitincorrect or inefficient circuit • Not necessarily synthesis tool's fault!Verilog for Digital DesignCopyright © 2007Frank Vahid and Roman Lysecky10HDLs for Synthesis• Consider the English language– General and complex; many uses–But use for cookingrecipes is greatly restrictedgpgy• Chef understands: stir, blend, eggs, bowl, ...• Chef may not understand: bludgeon, harmonic, forthright, castigate, ..., even if English grammar is correctIf the meal turns out bad don't blame the