Verilog for Digital DesignHigh-Level State Machine BehaviorSlide 3High-Level State Machine BehaviorSlide 5Slide 6Simulating the HLSMTop-Down Design— HLSM to Controller and DatapathTop-Down Design: HLSM to Controller and DatapathSlide 10Slide 11Slide 12Slide 13Describing a Datapath BehaviorallyDescribing the Controller BehaviorallyController and Datapath BehaviorDescribing a State Machine using One ProcessOne-Procedure State Machine DescriptionSlide 19Timing Differences Between Two and One Procedure DescriptionsOne Procedure FSM DescriptionImproving Timing RealismSlide 23Delay Control on Right Side of Assignment StatementsSimulation with Timing Delays AddedAlgorithmic-Level BehaviorSlide 27Algorithmic-Level Behavior for SADSlide 29Slide 30Event Control with an ExpressionSlide 32Top-Down Design – Converting Algorithmic-Level Behavior to RTLConvert Algorithm to HLSMDescribe HLSM in VerilogSlide 36Automated Synthesis from the Algorithmic LevelSimulation SpeedMemoryAccessing MemorySimple Memory EntitySlide 42Slide 43TestbenchWaveforms1Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyVerilog for Digital DesignChapter 5: RTL Design2Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyHigh-Level State Machine Behavior3Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyHigh-Level State Machine Behavior•Register-transfer level (RTL) design captures desired system behavior using high-level state machine–Earlier example – 3 cycles high, used FSM–What if 512 cycles high? 512-state FSM?–Better solution – High-level state machine that uses register to count cycles•Declare explicit register Cnt (2 bits for 3-cycles high)•Initialize Cnt to 2 (2, 1, 0  3 counts)•"On" state–Sets X=1–Configures Cnt for decrement on next cycle–Transitions to Off when Cnt is 0–Note that transition conditions use current value of Cnt, not next (decremented) value•For 512 cycles high, just initialize Cnt to 511Inputs: B; Outputs: XOn2On1 On3OfX=1X=1X=1X=0B'B3 cycles with X=1 Inputs: B; Outputs: X;OnOfX=1X=0B'B3 cycles with X=1 Register: Cnt(2)Cnt=2Cnt=Cnt-1(Cnt=0)'Cnt=04Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyCombinationallogicState registerStatexbclkFSMinputsFSMoutputsStateNextHigh-Level State Machine Behavior•Module ports same as FSM•Same two-procedure approach as FSM–One for combinational logic, one for registers–Registers now include explicit registers (Cnt)•Two reg variables per explicit register (current and next), just like for state register`timescale 1 ns/1 nsmodule LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On = 1; reg [0:0] State, StateNext; reg [1:0] Cnt, CntNext; // CombLogic always @(State, Cnt, B) begin ... end // Regs always @(posedge Clk) begin ... endendmodulevldd_ch5_LaserTimerHLSM.vCombinationallogicState registerStateXBClkHLSMinputsHLSMoutputsStateNextCnt registerCntCntNext5Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyHigh-Level State Machine Behavior•CombLogic process–Describes actions and transitions... reg [0:0] State, StateNext; reg [1:0] Cnt, CntNext; // CombLogic always @(State, Cnt, B) begin case (State) S_Off: begin X <= 0; CntNext <= 2; if (B == 0) StateNext <= S_Off; else StateNext <= S_On; end S_On: begin X <= 1; CntNext <= Cnt - 1; if (Cnt == 0) StateNext <= S_Off; else StateNext <= S_On; end endcase end...vldd_ch5_LaserTimerHLSM.vCombinationallogicState registerStateXBClkHLSMinputsHLSMoutputsStateNextCnt registerCntCntNextNote: Writes are to "next" variable, reads are from "current" variable. See target architecture to understand why.Inputs: B; Outputs: X;OnOfX=1X=0B'BRegister: Cnt(2)Cnt=2Cnt=Cnt-1(Cnt=0)'Cnt=06Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyHigh-Level State Machine Behavior•Regs process–Updates registers on rising clock... // Regs always @(posedge Clk) begin if (Rst == 1 ) begin State <= S_Off; Cnt <= 0; end else begin State <= StateNext; Cnt <= CntNext; end end...vldd_ch5_LaserTimerHLSM.vCombinationallogicState registerStateXBClkHLSMinputsHLSMoutputsStateNextCnt registerCntCntNextInputs: B; Outputs: X;OnOfX=1X=0B'BRegister: Cnt(2)Cnt=2Cnt=Cnt-1(Cnt=0)'Cnt=07Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckySimulating the HLSM•Use same testbench as in Chapter 3•Waveforms below also show Cnt and State variables, even though not a port on the LaserTime module–Simulators allow one to zoom into modules to select internal variables/nets to show•Note reset behavior–Until Rst=1 and rising clock, Cnt and State undefined–Upon Rst=1 and rising clock, Cnt set to 0, and State set to S_Off (which is defined as 0)•Note how system enters S_On on first rising clock after B becomes 1, causing Cnt to be initialized to 2–Cnt is decremented in S_On–Cnt wrapped from 0 to 3, but the 3 was never usedRstClkXBStateCntxXX1 for 3 cyclesInputs: B; Outputs: X;OnOfX=1X=0B'BRegister: Cnt(2)Cnt=2Cnt=Cnt-1(Cnt=0)'Cnt=08Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyTop-Down Design— HLSM to Controller and Datapath9Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyTop-Down Design: HLSM to Controller and Datapath•Recall from Chapters 2 & 3–Top-down design•Capture behavior, and simulate•Capture structure (circuit), simulate again•Gets behavior right first, unfettered by complexity of creating structureCapture behaviorSimulateW_sP_sS_sK_sCapture structureSimulateW_sP_sS_sK_sShould be the same10Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyTop-Down Design: HLSM to Controller and Datapath•Recall from Chapters 2 & 3–Top-down design•Capture behavior, and simulate•Capture structure (circuit), simulate again•Gets behavior right first, unfettered by complexity of creating structure•At RTL level–Capture behavior  HLSM–Capture structure: Controller and datapathController DatapathInputs: B; Outputs: X;OnOfX=1X=0B'BRegister: Cnt(2)Cnt=2Cnt=Cnt-1(Cnt=0)'Cnt=011Verilog for Digital DesignCopyright © 2007 Frank Vahid and Roman LyseckyTop-Down Design: HLSM to Controller and