ECE 5440/6370 Advanced Digital Design Spring 2010 1 Final Project, Part I: Keypad Scanner Due on April 29th, 11:59 pm Introduction: The objectives of Part I of the Final Project are: o RTL coding of a sequential state machine to implement a keypad scanner o Utilize Linear Feedback Shift Register (LFSR) counters o Utilize a BFM in the test bench o logic synthesis o place and route of the netlist for implementation in an FPGA o Thorough testing of the design in its RTL, gate-level netlist and hardware abstractions. Final Project, Part I Description: Design a state machine to scan and debounce a 16-key keypad. Use Verilog HDL to implement and verify the design. Use Modelsim for simulation and Quartus II for synthesis, place and route. Target the implementation to the Altera DE2 board to demonstrate that the scanner is fully functional. Use the 7-segment display resources of the DE2 board to display the number of keystrokes and the key value of the last key pressed. The block diagram below shows a typical partitioning of the logic. 16-Key Keypad Scanner Architecturescanner_corekeypadlfsr_cntrROW[3:0]COL[3:0]auto_readscanner_iosevenseg_enckey_cntr sevenseg_enckey_xlateKEY_DATA[3:0]KEY_RDYAUTO_RD_KEY_RD_KEY_7SEG[6:0]CNT_7SEG[6:0]CLOCKRESET_Note:ROW[3:0] is a tri-stateable outputTEST_ Figure 1: Block Diagram of Keypad ScannerECE 5440/6370 Advanced Digital Design Spring 2010 2 Scanner Core Logic Behavior: o The 16-key keypad (provided) is constructed in matrix fashion having 4 row and 4 column pins. To scan the keypad, the row pins are driven low (asserted) one at a time. In order to prevent potential signal contention, the row pins are driven using open drain outputs. The four column pins from the keypad are externally pulled up and are sampled periodically to determine if any keys on the selected (asserted) row are being pressed. A single scan is defined as the process of sequentially asserting each of the four row pins. o A key should not be recognized as pressed unless the following conditions are true: 1. After scanning the keyboard (all 16 keys) a minimum of 1 time, no keys are pressed. 2. One and only one key is consistently pressed for a minimum of 4 sequential scans. o The scan rate of the keypad should be adjusted such that a key will not be recognized in less than 8 milliseconds. o After a key is recognized as pressed, the state machine enters a unique state to signal the target system that a valid key is ready to be read. While in this state, the KEY_RDY signal is asserted. o The design should include a holding register for the key location (rowcol[3:0]) that indicates the row (bits 3 and 2) and column (bits 1 and 0) of the key that was pressed. At the conclusion of (single) scans 2, 3 and 4, it is not necessary or desirable to compare the location of a pressed key with that obtained during the first scan. It is not possible for the key location detected for the pressed key to change within the key recognition time-frame (8 msec). Thus, the key location stored during the last (4th) scan can be safely assumed to be the same value as the key location detected at during all other scans. o When the low-true (active low) KEY_RD_ signal is driven by the target system (in this case, your test module) the KEY_DATA[3:0] is captured. KEY_DATA[3:0] is the hexadecimal value corresponding to the label on the last key pressed. It is expected that the KEY_RD_ signal will stay asserted (low) until the KEY_RDY signal deasserts. o When the KEY_RD_ signal de-asserts (goes high), the state machine begins to look for no keys pressed (see bullet 2, statement 1). LFSR Counter: The purpose of the LFSR counter is to control the scan rate of the scanning. The total time from “key pressed” to “key recognized” should be no less than 8 milliseconds so as to mask any bouncing that may be taking place. For example, assume the following: 1) the scanner has 4 rows 2) the scanner scans the keypad 4 times before recognizing a key 3) the LFSR clock frequency is 1 MHz Then the counter length (number of clocks before timeout) would be (8.0 E-3 * 1.0 E6) / (4 * 4) = 500. Therefore, an LFSR counter having a length of 9 bits would be appropriate. THE FORMULA VALUES STATED ABOVE ARE CONSISTANT WITH THE EXAMPLE. You will have to recalculate the counter length for your lab design based on the DE2 board 50MHz clock source. The LFSR counter module actually has two instances of LFSR counters. The LFSR module has one decoded output (counter time out) from each of its LFSR counters. The two decoded outputs are 1) lfsr_lto and 2) lfsr_sto. The lto signal is a “long” counter timeout that will yield an 8 msec key recognition time. The sto signal should decode a shorter, 15-state LFSR counter. The scanner_core module selects the lto or sto signal depending on whether the design is in test mode or not. Use test mode (TEST_ low) for all of your simulations. Use non-test mode (TEST_ high) for demonstrations on the DE2 board. The LFSR counters should be asynchronously reset by the RESET_ signal and synchronously cleared by lfsr_en. Key_cntr: The key_cntr module contains a synchronous binary counter that is asynchronously reset by RESET_. This counter increments each time KEY_RDY asserts. The challenge is to clock this counter using the CLOCK input. It is considered bad practice for synchronous digital designs to clock flip flops directly from non-clock signals. Therefore, using “posedge KEY_RDY” is not permitted.ECE 5440/6370 Advanced Digital Design Spring 2010 3 Key_xlate: The key_xlate module translates the row/column code generated by the core logic to a 4-bit key value code that corresponds to the hexadecimal key label for each of the 16 keys. This module is comprised of purely combinatorial logic. Sevenseg_enc: This module encodes 4 bits of binary information into a 7-bit pattern suitable for driving one of the 7-segment LED displays contained on the DE2 board. Each of the 7-segment display segments will light when its associated FPGA pin is driven low. Refer to the DE2 board user manual for the pin assignments for the 7-segment devices. Auto Read: The schematic diagram for this module illustrated in Figure 2. This module is a small state machine that generates a read pulse whenever the o_key_rdy signal asserts. When the AUTO_RD_ pin is connected to the KEY_RD_ pin, KEY_DATA is assumed to be captured by the