Chapter 6: Datapath and Control6-1CPSC 352 Chapter 6: Datapath and ControlChapter 6: Datapath and Control6-2CPSC 352Chapter Contents6.1 Basics of the Microarchitecture6.2 A Microarchitecture for the ARC6.3 Hardwired Control6.4 Case Study: The VHDL Hardware Description LanguageChapter 6: Datapath and Control6-3CPSC 352The Fetch-Execute Cycle• The steps that the control unit carries out in executing a programare:(1) Fetch the next instruction to be executed from memory.(2) Decode the opcode.(3) Read operand(s) from main memory, if any.(4) Execute the instruction and store results.(5) Go to step 1.Chapter 6: Datapath and Control6-4CPSC 352High Level View of MicroarchitectureControl UnitControl SectionRegistersALUDatapath(Data Section)SYSTEM BUS• The microarchitecture consists of the control unit and the pro-grammer-visible registers, functional units such as the ALU,and any additional registers that may be required by the con-trol unit.Chapter 6: Datapath and Control6-5CPSC 352ARC Instruction Subsetld Load a register from memoryMnemonic MeaningstsethiandccaddcccalljmplbeorccornccStore a register into memoryLoad the 22 most significant bits of a registerBitwise logical ANDAddBranch on overflowCall subroutineJump and link (return from subroutine call)Branch if equalBitwise logical ORBitwise logical NORbnegbcsBranch if negativeBranch on carrysrl Shift right (logical)bvsba Branch alwaysMemoryLogicArithmeticControlChapter 6: Datapath and Control6-6CPSC 352ARC Instruction Formatsop3 (op=10)010000010001010010010110100110111000addccandccorccornccsrljmpl00010101011001111000condbebcsbnegbvsbabranch010100op2branchsethiInst.00011011opSETHI/BranchCALLArithmeticMemoryFormat000000000100ldstop3 (op=11)opCALL formatdisp3031 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0001SETHI Formatimm2231 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00rddisp220 cond0000Branch Formatop2op231 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00rs11 op3simm131 op31Memory Formats1rdrdrs10100000000 rs2Arithmetic Formats31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00rs11 op3simm131 op300rdrdrs10100000000 rs2iPSR31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00zvcnChapter 6: Datapath and Control6-7CPSC 352 ARC Datapath%r0A bus B busC busF1F2ALU32324%r164-to-32 MUXC Bus MUXn, z, v, cF0C Decoder%r5%pc%temp0%r2%r3%r4%r6%r7%r8%r9%r10%r30%r31B DecoderF36c1c373738b0b376A Decoder38a0a376Data From Main MemoryMUX Control Line (From Control Unit)%temp1%temp2%temp3%irData To Main MemoryAddress To Main MemoryCLOCK UNIT012345678910303132333435363732From Control UnitFrom Control UnitSet Condition Codes (SCC)3232...To Control Unit24Chapter 6: Datapath and Control6-8Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringARC ALU Operations00110011001100110101010101010101F1F0ANDCC (A, B)ORCC (A, B)NORCC (A, B)ADDCC (A, B)SRL (A, B)AND (A, B)OR (A, B)NOR (A, B)ADD (A, B)LSHIFT2 (A)LSHIFT10 (A)SIMM13 (A)SEXT13 (A)INC (A)INCPC (A)RSHIFT5 (A)Operation0000111100001111F2Changes Condition Codesyesyesyesyesnononononononononononono0000000011111111F3Chapter 6: Datapath and Control6-9Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringBlockDiagramof ALUALU LUT0b0a0ALU LUT1b1a1ALU LUT30b30a30ALU LUT31b31a31Cc0c1c30c31carryBARREL SHIFTERz0z1z30z31. . .F0:3Barrel Shifter Control LUTb0-4Direction of ShiftShift Amount (SA)5NV Z. . .SCC: Set Condition CodesF3F202444Chapter 6: Datapath and Control6-10Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringGate-Level Layout of Barrel Shifterc31c30c1c0SA0. . .Shift RightSA1. . .Shift Right...Bit 31 Bit 30 Bit 1 Bit 0Bit 29 Bit 28Bit 3 Bit 2Bit 29Bit 2Chapter 6: Datapath and Control6-11Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringTruth Table for (Most of the) ALU LUTsF300000000000000F200000000000000F100000000000000F000000000111111Carry In00001111000011...ai00110011001100bi01010101010101zi00010001011101Carry Out00000000000000...ANDCCORCCChapter 6: Datapath and Control6-12Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringDesign of Register %r1CLKQDC31Write select (from c1 bit of C Decoder)A31B31QDC30A30B30QDC0A0B0. . .. . .A bus enable (from a1 bit of A Decoder)B bus enable (from b1 bit of B Decoder). . .Data inputs from C BusData outputs to B BusData outputs to A BusChapter 6: Datapath and Control6-13Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringOutputs to Control Unit fromRegister %irData inputs from C Bus313029282726252423222120191817161514131211109876543210Instruction fieldsC0C31Instruction Register %iropop2op3rd rs1 rs2bit 13Chapter 6: Datapath and Control6-14Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringMicroarch-itecture ofthe ARC32A busB busC bus2048 word × 41 bit Control StoreCS Address MUXJumpControl branch logic (CBL)F1F2ALUMicrocode Instruction Register (MIR)CLOCK UNIT411111MAIN MEMORYWRRDData Section (Datapath)32AddressData In00 = Next01 = Jump10 = Inst. Dec.482Decode1004232 byte address space323Data Out64-to-32 MUXC Bus MUX%psrn, z, v, cF0Next11Control Store Address Incrementer (CSAI)Acknowledge (ACK)To C Decoder%irC MUX0, rdControl SectionA MUX0, rs1To B DecoderB MUX0, rs2F341IR[30,31,19-24]6 56MIR C fieldSelectMIR A fieldMIR B field665 6SelectSelectScratchpadTo A Decoderrd rs2 rs1 opsIR[13]5 6Set Condition Codes%irRDWRCA B JUMP ADDRALUCONDAMUXBMUXCMUXChapter 6: Datapath and Control6-15Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringMicroword FormatRDWRCA B JUMP ADDRALUCONDAMUXBMUXCMUXChapter 6: Datapath and Control6-16Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. HeuringSettings for the COND Field of theMicroword0011001101010101C1C0Use NEXT ADDRUse JUMP ADDR if n = 1Use JUMP ADDR if z = 1Use JUMP ADDR if v = 1Use JUMP ADDR if c = 1Use JUMP ADDR if IR[13] = 1Use JUMP ADDRDECODEOperation00001111C2Chapter 6: Datapath and Control6-17Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and