Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 7: MemoryChapter ContentsThe Memory HierarchyFunctional Behavior of a RAM CellSimplified RAM Chip PinoutA Four-Word Memory with Four Bits per Word in a 2D OrganizationA Simplified Representation of the Four-Word by Four-Bit RAM2-1/2D Organization of a 64-Word by One-Bit RAMTwo Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight-Bit RAMTwo Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAMSingle-In-Line Memory ModuleA ROM Stores Four Four-Bit WordsA Lookup Table (LUT) Implements an Eight-Bit ALUPlacement of Cache in a Computer SystemAn Associative Mapping Scheme for a Cache MemoryAssociative Mapping ExampleReplacement PoliciesA Direct Mapping Scheme for Cache MemoryDirect Mapping ExampleA Set Associative Mapping Scheme for a Cache MemorySet-Associative Mapping ExampleCache Read and Write PoliciesHit Ratios and Effective Access TimesDirect Mapped Cache ExampleTable of Events for Example ProgramCalculation of Hit Ratio and Effective Access Time for Example ProgramNeat Little LRU AlgorithmOverlaysVirtual MemoryPage TableUsing the Page TableUsing the Page Table (cont’)SegmentationFragmentationTranslation Lookaside Buffer3-Variable DecoderTree Decoder - 3 VariablesTree Decoding – One Level at a TimeContent Addressable Memory – AddressingOverview of CAMAddressing Subtrees for a CAMBlock Diagram of Dual-Read RAMRambus MemoryThe Intel Pentium Memory System7-1Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationPrinciples of Computer ArchitectureMiles Murdocca and Vincent HeuringChapter 7: Memory7-2Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationChapter Contents7.1 The Memory Hierarchy7.2 Random Access Memory7.3 Chip Organization7.4 Commercial Memory Modules7.5 Read-Only Memory7.6 Cache Memory7.7 Virtual Memory7.8 Advanced Topics7.9 Case Study: Rambus Memory7.10 Case Study: The Intel Pentium Memory System7-3Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe Memory Hierarchy7-4Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationFunctional Behavior of a RAM Cell7-5Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationSimplified RAM Chip Pinout7-6Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationA Four-Word Memory with Four Bits per Word in a 2D Organization7-7Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationA Simplified Representation of the Four-Word by Four-Bit RAM7-8Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer Organization2-1/2D Organization of a 64-Word by One-Bit RAM7-9Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationTwo Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight-Bit RAM7-10Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationTwo Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM7-11Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationSingle-In-Line Memory Module• Adapted from(Texas Instruments, MOS Memory: Commercial and Military Specifications Data Book, Texas Instruments, Literature Response Center, P.O. Box 172228, Denver, Colorado, 1991.)7-12Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationA ROM Stores Four Four-Bit Words7-13Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationA Lookup Table (LUT) Implements an Eight-Bit ALU7-14Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationPlacement of Cache in a Computer System• The locality principle: a recently referenced memory location is likely to be referenced again (temporal locality); a neighbor of a recently referenced memory location is likely to be referenced (spatial locality).7-15Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationAn Associative Mapping Scheme for a Cache Memory7-16Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationAssociative Mapping Example• Consider how an access to memory location (A035F014)16is mapped to the cache for a 232word memory. The memory is divided into 227blocks of 25= 32 words per block, and the cache consists of 214slots:• If the addressed word is in the cache, it will be found in word (14)16of a slot that has tag (501AF80)16, which is made up of the 27 most significant bits of the address. If the addressed word is not in the cache, then the block corresponding to tag field (501AF80)16is brought into an available slot in the cache from the main memory, and the memory reference is then satisfied from the cache.7-17Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationReplacement Policies• When there are no available slots in which to place a block, a replacement policy is implemented. The replacement policy governs the choice of which slot is freed up for the new block.• Replacement policies are used for associative and set-associative mapping schemes, and also for virtual memory.• Least recently used (LRU)• First-in/first-out (FIFO)• Least frequently used (LFU)•Random• Optimal (used for analysis only – look backward in time and reverse-engineer the best possible strategy for a particular sequence of memory references.)7-18Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationA Direct Mapping Scheme for Cache Memory7-19Chapter 7 - MemoryDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationDirect Mapping Example• For a direct mapped cache, each main memory block can be mapped to only one slot, but each slot can receive more than oneblock. Consider how an access to memory location (A035F014)16is mapped to the cache for a 232word memory. The memory is divided into 227blocks of 25= 32 words per block, and the cache